June 2008
HYS64T128000EU–[19F/1.9/25F/2.5/3S]–C2
HYS72T128000EU–[25F/2.5/3S]–C2
HYS64T256020EU–[19F/1.9/25F/2.5/3S]–C2
HYS72T256020EU–[25F/2.5/3S]–C2
240-Pin Unbuffered DDR2 SDRAM Modules
UDIMM SDRAM
EU RoHS Compliant
Internet Data Sheet
Rev. 1.00
Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[19F/1.9/25F/2.5/3S]–C2
Unbuffered DDR2 SDRAM Modules
HYS64T128000EU–[19F/1.9/25F/2.5/3S]–C2, HYS72T128000EU–[25F/2.5/3S]–C2, HYS64T256020EU–
[19F/1.9/25F/2.5/3S]–C2, HYS72T256020EU–[25F/2.5/3S]–C2
Revision History: 2008-06, Rev. 1.00
Page
All
Subjects (major changes since last revision)
Added product type HYS64T[128/256]0x0-[19F/1.9]-C2 and removed product type HYS64T[128/256]0x0-3-C2
and adapted to internet edition.
IDD values updated.
New Document.
Previous Revision: Rev. 0.51, 2007-11
30-34
All
Previous Revision: Rev. 0.50, 2007-10
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_A4, 4.20, 2008-01-25
12032007-I9KE-FFWO
2
Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[19F/1.9/25F/2.5/3S]–C2
Unbuffered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 240-pin Unbuffered DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh.
Auto Refresh for temperatures above 85 °C
t
REFI
= 3.9
μs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible.
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT).
Serial Presence Detect with E
2
PROM.
UDIMM and EDIMM Dimensions (nominal): 30 mm high,
133.35 mm wide
Based on standard reference layouts Raw Cards 'D', 'E', 'F'
and 'G'.
RoHS compliant products
1)
.
• 240-Pin PC2-8500, PC2-6400 and PC2-5300 DDR2
SDRAM memory modules.
• One rank 128M
×
64, 128M
×
72, and two rank 256M
×
64,
256M
×
72 module organization, and 128M
×
8 chip
organization.
• 2GB, 1GB Modules built with 1 Gbit DDR2 SDRAMs in
chipsize packages PG-TFBGA-60.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5, 6, 7 and 8 ), Burst
Length (8 & 4).
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL4
CL5
CL6
CL7
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
DDR2
PC2
–19F
–1066E
–8500E
6–6–6
–1.9
–1066F
–8500F
7–7–7
–
266
333
400
533
13.125
13.125
45
–25F
–800D
–6400D
5–5–5
200
266
400
–
–
12.5
12.5
45
–2.5
–800E
–6400E
6–6–6
200
266
333
400
–
15
15
45
–3S
–667D
–5300D
5–5–5
200
266
333
–
–
15
15
45
Unit
Note
t
CK
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
f
CK3
f
CK4
f
CK5
f
CK6
f
CK7
t
RCD
t
RP
t
RAS
–
333
400
533
533
11.25
11.25
45
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products
.
Rev. 1.00, 2008-06
12032007-I9KE-FFWO
3
Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[19F/1.9/25F/2.5/3S]–C2
Unbuffered DDR2 SDRAM Modules
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Min. Row Cycle Time
DDR2
PC2
–19F
–1066E
–8500E
6–6–6
–1.9
–1066F
–8500F
7–7–7
58.125
–25F
–800D
–6400D
5–5–5
57.5
–2.5
–800E
–6400E
6–6–6
60
–3S
–667D
–5300D
5–5–5
60
Unit
Note
t
CK
ns
1)2)
Precharge-All (8 banks) command
13.125
15
15
17.5
18
ns
period
1) This
t
PREA
value is the minimum value at which this chip will be functional.
2) Precharge-All command for an 8 bank device will equal to
t
RP
+ 1 ×
t
CK
or
t
nRP
+ 1 × nCK, depending on the speed bin,
where
t
nRP
= RU{
t
RP
/
t
CK(avg)
} and
t
RP
is the value for a single bank precharge.
t
RC
t
PREA
56.25
1.2
Description
The memory array is designed with 1 Gbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The
Qimonda
HYS[64/72]T[128/256]0x0EU–
[19F/1.9/25F/2.5/3S]–C2
module
family
are
Unbuffered DIMM modules “UDIMMs” with 30 mm height
based on DDR2 technology. DIMMs are available as non-
ECC modules in 128M
×
64 (1GB), 256M
×
64 (2GB) and as
ECC modules in 128M
×
72 (1GB), 256M
×
72 (2GB) in
organization and density, intended for mounting into 240-pin
connector sockets.
TABLE 2
Ordering Information
Product Type
1)
PC2-8500 (6-6-6)
HYS64T256020EU-19F-C2
2GB 2R×8 PC2–8500U–666–13–E0
HYS64T128000EU-19F-C2
1GB 1R×8 PC2–8500U–666–13–D0
PC2-8500 (7-7-7)
HYS64T256020EU-1.9-C2
HYS64T128000EU-1.9-C2
PC2-6400 (5-5-5)
HYS64T256020EU-25F-C2
2GB 2R×8 PC2–6400U–555–12–E0
HYS72T256020EU-25F-C2
2GB 2R×8 PC2–6400E–555–12–G0
HYS64T128000EU-25F-C2
1GB 1R×8 PC2–6400U–555–12–D0
HYS72T128000EU-25F-C2
1GB 1R×8 PC2–6400E–555–12–F0
PC2-6400 (6-6-6)
HYS64T256020EU-2.5-C2
HYS72T256020EU-2.5-C2
HYS64T128000EU-2.5-C2
2GB 2R×8 PC2–6400U–666–12–E0
2GB 2R×8 PC2–6400E–666–12–G0
1GB 1R×8 PC2–6400U–666–12–D0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Rank, Non-ECC
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
2 Ranks, Non-ECC
2 Ranks, ECC
1 Rank, Non-ECC
1 Rank, ECC
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
2GB 2R×8 PC2–8500U–777–13–E0
1GB 1R×8 PC2–8500U–777–13–D0
2 Ranks, Non-ECC
1 Rank, Non-ECC
1Gbit (×8)
1Gbit (×8)
2 Ranks, Non-ECC
1 Rank, Non-ECC
1Gbit (×8)
1Gbit (×8)
Compliance Code
2)
Description
SDRAM Technology
Rev. 1.00, 2008-06
12032007-I9KE-FFWO
4
Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[19F/1.9/25F/2.5/3S]–C2
Unbuffered DDR2 SDRAM Modules
Product Type
1)
HYS72T128000EU-2.5-C2
PC2-5300 (5-5-5)
HYS64T256020EU-3S-C2
HYS72T256020EU-3S-C2
HYS64T128000EU-3S-C2
HYS72T128000EU-3S-C2
Compliance Code
2)
1GB 1R×8 PC2–6400E–666–12–F0
2GB 2R×8 PC2–5300U–555–12–E0
2GB 2R×8 PC2–5300E–555–12–G0
1GB 1R×8 PC2–5300U–555–12–D0
1GB 1R×8 PC2–5300E–555–12–F0
Description
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
1 Rank, Non-ECC
1 Rank, ECC
SDRAM Technology
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–8500U–666–13–D0" where 8500U
means Unbuffered DIMM modules with Module Bandwidth and "666–13" means Column Address Strobe (CAS) latency =6, Row Column
Delay (RCD) latency = 6 and Row Precharge (RP) latency = 6 using the Industry Standard SPD Revision 1.3 and produced on the Raw
Card "D".
TABLE 3
Address Format
DIMM
Density
2GB
2GB
1GB
1GB
Module
Organization
256M
×
64
256M
×
72
128M
×
64
128M
×
72
Memory
Ranks
2
2
1
1
ECC/
Non-ECC
Non-ECC
ECC
Non-ECC
ECC
# of SDRAMs # of row/bank/column
bits
16
18
8
9
14/3/10
14/3/10
14/3/10
14/3/10
Raw
Card
E
G
D
F
TABLE 4
Components on Modules
Product Type
1)2)
HYS72T256020EU
HYS64T256020EU
HYS72T128000EU
HYS64T128000EU
DRAM Components
1)
HYB18T1G800C2F
HYB18T1G800C2F
HYB18T1G800C2F
HYB18T1G800C2F
DRAM Density
1Gbit
1Gbit
1Gbit
1Gbit
DRAM Organisation
128M
×
8
128M
×
8
128M
×
8
128M
×
8
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.00, 2008-06
12032007-I9KE-FFWO
5
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