Datasheet> 器件分类 > 存储> 存储> HYMP125S64CP6-S6

文档预览

HYMP125S64CP6-S6: 产品描述DDR DRAM Module, 256MX64, 0.4ns, CMOS, ROHS COMPLIANT, SODIMM-200; 产品类别存储存储; 文件大小535KB，共23页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/; 标准

下载文档详细参数选型对比全文预览

HYMP125S64CP6-S6概述

DDR DRAM Module, 256MX64, 0.4ns, CMOS, ROHS COMPLIANT, SODIMM-200

HYMP125S64CP6-S6规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	SK Hynix(海力士)
零件包装代码	MODULE
包装说明	ROHS COMPLIANT, SODIMM-200
针数	200
Reach Compliance Code	compliant
ECCN代码	EAR99
最长访问时间	0.4 ns
其他特性	AUTO/SELF REFRESH
JESD-30 代码	R-XDMA-N200
内存密度	17179869184 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	64
功能数量	1
端口数量	1
端子数量	200
字数	268435456 words
字数代码	256000000
工作模式	SYNCHRONOUS
最高工作温度	65 °C
最低工作温度
组织	256MX64
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
自我刷新	YES
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED

文档预览

下载PDF文档

全文
预览

200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb version C

This Hynix unbuffered Small Outline Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2

SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb version C based

Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-

try standard. It is suitable for easy interchange and addition.

FEATURES

•

JEDEC standard Double Data Rate 2 Synchronous

DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power

Supply

•

All inputs and outputs are compatible with SSTL_1.8

interface

•

Posted CAS

Programmable CAS Latency 3 ,4 ,5, and 6

OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

•

Fully differential clock operations (CK & CK)

•

Programmable Burst Length 4 / 8 with both

sequential and interleave mode

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial presence detect with EEPROM

DDR2 SDRAM Package: 60 ball(x8) , 84 ball(x16)

FBGA

•

67.60 x 30.00 mm form factor

RoHS compliant

ORDERING INFORMATION

Part Name

HYMP164S64CP6-C4/Y5/S5/S6

HYMP112S64CP6-C4/Y5/S5/S6

HYMP125S64CP8-C4/Y5/S5/S6

Density

512MB

1GB

2GB

Organization

64Mx64

128Mx64

256Mx64

# of

DRAMs

# of

ranks

Materials

Lead free

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.7 / Jan. 2008

1200pin

Unbuffered DDR2 SDRAM SO-DIMMs

PIN DESCRIPTION

Symbol

Type

Polarity

Cross

Point

Pin Description

The system clock inputs. All adress an commands lines are sampled on the cross point

CK[1:0], CK[1:0]

Input

of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is

driven from the clock inputs and output timing for read operations is synchronized to

the input clock.

CKE[1:0]

Input

Active

High

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when

low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self

Refresh mode.

Enables the associated DDR2 SDRAM command decoder when low and disables the

S[1:0]

Input

Active

Low

Active

Low

command decoder when high. When the command decoder is disabled, new commands

are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is

selected by S1

RAS, CAS, WE

BA[2:0]

ODT[1:0]

Input

Active

High

When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS,

RAS and WE define the operation to be excecuted by the SDRAM.

Selects which DDR2 SDRAM internal bank of four or eight is activated.

Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2

SDRAM mode register.

During a Bank Activate command cycle, difines the row address when sampled at the

cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-

mand cycle, defines the column address when sampled at the cross point of the rising

edge of CK and falling edge of CK. In addition to the column address, AP is used to

A[9:0], A10/AP,

A[15:11]

Input

invoke autoprecharge operation at the end of the burst read or write cycle. If AP is

high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP

is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in

conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks

will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn

are used to define which bank to precharge.

DQ[63:0]

DM[7:0]

In/Out

Input

Active

High

Data Input/Output pins.

The data write masks, associated with one data byte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation

if it is high. In Read mode, DM lines have no effect.

The data strobe, associated with one data byte, sourced whit data transfers. In Write

mode, the data strobe is sourced by the controller and is centered in the data window.

DQS[7:0], DQS[7:0] In/Out

Cross

point

In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading

edge of the data window. DQS signals are complements, and timing is relative to the

crosspoint of respective DQS and DQS. If the module is to be operated in single ended

strobe mode, all DQS signals must be tied on the system board to VSS and DDR2

SDRAM mode registers programmed approriately.

, V

SPD,V

SDA

SCL

SA[1:0]

TEST

Supply

In/Out

Input

In/Out

Power supplies for core, I/O, Serial Presense Detect, and ground for the module.

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A

resister must be connected to V

DD t

o act as a pull up.

This signals is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from SCL to VDD to act as a pull up.

Address pins used to select the Serial Presence Detect base address.

The TEST pin is reserved for bus analysis tools and is not connected on normal memory

modules(SODIMMs).

Rev. 0.7 / Jan. 2008

HYMP125S64CP6-S6相似产品对比

	HYMP125S64CP6-S6	HYMP125S64CP6-S5	HYMP125S64CP6-Y5	HYMP125S64CP6-C4
描述	DDR DRAM Module, 256MX64, 0.4ns, CMOS, ROHS COMPLIANT, SODIMM-200	DDR DRAM Module, 256MX64, 0.4ns, CMOS, ROHS COMPLIANT, SODIMM-200	DDR DRAM Module, 256MX64, 0.45ns, CMOS, ROHS COMPLIANT, SODIMM-200	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SODIMM-200
是否Rohs认证	符合	符合	符合	符合
厂商名称	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	MODULE	MODULE	MODULE	MODULE
包装说明	ROHS COMPLIANT, SODIMM-200	ROHS COMPLIANT, SODIMM-200	ROHS COMPLIANT, SODIMM-200	ROHS COMPLIANT, SODIMM-200
针数	200	200	200	200
Reach Compliance Code	compliant	compliant	compliant	compli
ECCN代码	EAR99	EAR99	EAR99	EAR99
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 代码	R-XDMA-N200	R-XDMA-N200	R-XDMA-N200	R-XDMA-N200
内存密度	17179869184 bit	17179869184 bit	17179869184 bit	17179869184 bi
内存集成电路类型	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
内存宽度	64	64	64	64
功能数量	1	1	1	1
端口数量	1	1	1	1
端子数量	200	200	200	200
字数	268435456 words	268435456 words	268435456 words	268435456 words
字数代码	256000000	256000000	256000000	256000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	65 °C	65 °C	65 °C	65 °C
组织	256MX64	256MX64	256MX64	256MX64
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	DIMM	DIMM	DIMM	DIMM
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
自我刷新	YES	YES	YES	YES
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	NO LEAD	NO LEAD	NO LEAD	NO LEAD
端子位置	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
最长访问时间	0.4 ns	0.4 ns	0.45 ns	-

HYMP125S64CP6-S6

HYMP125S64CP6-S6概述

HYMP125S64CP6-S6规格参数

文档预览

HYMP125S64CP6-S6相似产品对比

推荐资源