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IDT23S05-1HDCGI

产品描述PLL Based Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8
产品类别逻辑    逻辑   
文件大小59KB,共8页
制造商IDT (Integrated Device Technology)
标准
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IDT23S05-1HDCGI概述

PLL Based Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8

IDT23S05-1HDCGI规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
零件包装代码SOIC
包装说明SOP, SOP8,.25
针数8
Reach Compliance Codecompli
ECCN代码EAR99
输入调节STANDARD
JESD-30 代码R-PDSO-G8
JESD-609代码e3
长度4.9 mm
逻辑集成电路类型PLL BASED CLOCK DRIVER
最大I(ol)0.032 A
湿度敏感等级1
功能数量1
反相输出次数
端子数量8
实输出次数4
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装等效代码SOP8,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)260
电源3.3 V
传播延迟(tpd)0.35 ns
认证状态Not Qualified
Same Edge Skew-Max(tskwd)0.25 ns
座面最大高度1.7272 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
温度等级INDUSTRIAL
端子面层Matte Tin (Sn) - annealed
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间30
宽度3.9 mm
最小 fmax133 MHz
Base Number Matches1

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IDT23S05
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK
BUFFER, SPREAD SPECTRUM
COMPATIBLE
FEATURES:
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Output Skew < 250ps
Low jitter <200 ps cycle-to-cycle
IDT23S05-1 for Standard Drive
IDT23S05-1H for High Drive
No external RC network required
Operates at 3.3V V
DD
Power down mode
Spread spectrum compatible
Available in SOIC package
IDT23S05
DESCRIPTION:
The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT23S05 is an 8-pin version of the IDT23S09. IDT23S05 accepts
one reference input, and drives out five low skew clocks. The -1H version
of this device operates up to 133MHz frequency and has a higher drive than
the -1 device. All parts have on-chip PLLs which lock to an input clock on
the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT23S05 enters power down.
In this mode, the device will draw less than 12µA for Commercial Tempera-
ture range and less than 25µA for Industrial temperature range
,
the outputs
are tri-stated, and the PLL is not running, resulting in a significant reduction
of power.
The IDT23S05 is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
8
CLKOUT
REF
1
PLL
Control
Logic
3
CLK1
2
CLK2
5
7
CLK3
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2003
Integrated Device Technology, Inc.
OCTOBER 2003
DSC 6381/6

 
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