D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
®
HIP4083
Data Sheet
February 2003
FN4223.1
80V, 300mA Three Phase High Side Driver
The HIP4083 is a three phase high side N-channel MOSFET
driver, specifically targeted for PWM motor control. Two
HIP4083 may be used together for 3 phase full bridge
applications (see application block diagram). Alternatively,
the lower gates may be controlled directly from a buffered
microprocessor output.
Unlike other members of the HIP408x family, the HIP4083
has no built in turn-on delay. Each output (AHO, BHO, and
CHO) will turn-on 65ns after its input is switched low.
Likewise, each output will turn-off 60ns after its input is
switched high. Very short and very long dead times are
possible when two HIP4083 are used to drive a full bridge.
This dead time is controlled by the input signal timing.
The HIP4083 does not have a built in charge pump.
Therefore, the bootstrap capacitors must be recharged on a
periodic basis by initiating a short refresh pulse. In most
bridge applications, this will happen automatically every time
the lower FETs turn-on and the upper FETs turn-off.
However, it is still possible to use the HIP4083 in applications
that require the high side FETs to be on for extended periods
of time. This can be easily accomplished by sending a short
refresh pulse to the DIS pin.
The HIP4083 has reduced drive current compared to the
HIP4086 making it ideal for low to moderate power
applications. The HIP4083 is optimized for applications
where size and cost are important. For high power
applications driving large power FETs, the HIP4086 is
recommended.
Features
• Independently Drives Three High Side N-Channel
MOSFETs in Three Phase Bridge Configuration
• Bootstrap Supply Max Voltage to 95VDC
• Bias Supply Operation from 7V to 15V
• Drives 1000pF Load with Typical Rise Times of 35ns and
Fall Times of 30ns
• CMOS/TTL Compatible Inputs
• Programmable Undervoltage Protection
Applications
• Brushless Motors
• High Side Switches
• AC Motor Drives
• Switched Reluctance Motor Drives
Ordering Information
PART NUMBER
HIP4083AB
HIP4083AP
TEMP.
RANGE (
o
C)
-40 to 105
-40 to 105
PACKAGE
16 Ld SOIC
16 Ld PDIP
PKG. NO.
M16.15
E16.3
Pinout
HIP4083
(PDIP, SOIC)
TOP VIEW
AHI
BHI
CHI
DIS
V
SS
AHB
AHO
AHS
1
2
3
4
5
6
7
8
16 CHB
15 CHO
14 CHS
13 UVLO
12 V
DD
11 BHB
10 BHO
9 BHS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP4083
Application Block Diagram
80V
12V
AHI
BHI
HIP4083
CHI
CHO
AHO
BHO
MICRO-
CONTROLLER
(OPTIONAL)
AHI
BHI
GND
12V
AHO
BHO
HIP4083
CHI
CHO
GND
GND
Functional Block Diagram
6
DRIVER
LEVEL
SHIFTER
AHI
1
UV
7
8
6
BHI
2
LOGIC
CHI
DIS
3
4
LEVEL
SHIFTER
UV
EN
DRIVER
LEVEL
SHIFTER
UVLO 13
V
DD
12
UNDERVOLTAGE
DETECTOR
UV
UV
7
8
AHO
AHS
DRIVER
7
8
6
AHO
AHS
AHB
AHO
AHS
AHB
AHB
2
HIP4083
TRUTH TABLE
INPUT
AHI, BHI, CHI
X
X
1
0
NOTE:
X signifies that input can be either a “1” or “0”.
UV
1
X
0
0
DIS
X
1
0
0
OUTPUT
AHO, BHO, CHO
0
0
0
1
Typical Application: Three Phase Bridge Driver with Programmable Dead Time
CHIP SUPPLY
C
BYPASS
1 AHI
OPTIONAL
MICROPROCESSOR
INPUTS
2 BHI
3 CHI
4 DIS
5 V
SS
6 AHB
7 AHO
C
BS
8 AHS
CHB 16
CHO 15
CHS 14
UVLO 13
V
DD
12
BHB 11
BHO 10
BHS 9
OC SENSE
R
CURRENT
SENSE
POWER BUS
C
BS
C
BS
1 AHI
OPTIONAL
MICROPROCESSOR
INPUTS
2 BHI
3 CHI
4 DIS
5 V
SS
6 AHB
7 AHO
8 AHS
CHB 16
CHO 15
CHS 14
UVLO 13
V
DD
12
BHB 11
BHO 10
BHS 9
3-PHASE
LOAD
3
HIP4083
Typical Application: High Side Switch
BOOT STRAP CAPACITOR
80V
AND DIODE REQUIRED
REFRESH
12V
DIS
MICRO-
PROCESSOR
AHI
BHI
CHI
GND
HIP4083
AHO
BHO
CHO
LIGHT
Pin Descriptions
PIN
NUMBER
6
11
16
SYMBOL
AHB
BHB
CHB
(xHB)
AHI
BHI
CHI
(xHI)
V
SS
UVLO
DESCRIPTION
Gate driver supplies. One external bootstrap diode and one capacitor are required for each. The bootstrap diode
and capacitor may be omitted when the HIP4083 is used to drive the lower gates in three phase full bridge
applications. In this case, tie all three xHB pins to V
DD
and tie the xHS pins to the sources of the lower FETs. In
full bridge applications, the lower FETs must be turned on first at start up to refresh the bootstrap capacitors. In
high side switch applications, the load will keep xHS low and refresh should happen automatically at start up.
Logic level inputs. Logic at these three pins controls the three output drivers, AHO, BHO and CHO. When xHI is
low, xHO is high. When xHI is high, xHO is low. DIS (Disable) overrides all input signals. xHI can be driven by signal
levels of 0V to 15V (no greater than V
DD
).
Chip ground.
Undervoltage setting. A resistor can be connected between this pin and V
SS
to program the under voltage set point
- see Figure 7. With this pin not connected the undervoltage set point is typically 7V. When this pin is tied to V
DD
,
the undervoltage set point is typically 6.2V.
Disable input. Logic level input that when taken high sets all three outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to
15V (no greater than V
DD
).
Gate connections. Connect to the gates of the power MOSFETs in each phase.
1
2
3
5
13
4
DIS
7
10
15
8
9
14
AHO
BHO
CHO
(xHO)
AHS
BHS
CHS
(xHS)
MOSFET source connection. Connect the sources of the power MOSFETs and the negative side of the bootstrap
capacitors to these pins. In high side switch applications, 2mA of current will flow out of these pins into the load
when the upper FETs are off. This current is necessary to guarantee that the upper FETs stay off. This current
tends to pull xHS high. For proper refresh, the load must pull the voltage on xHS down to at least 7V below V
DD
.
For example, when V
DD
= 12V, xHS must be pulled down to 5V. Therefore, the minimum load necessary for proper
refresh is given by the following equation: R
MIN
= 5V/2mA = 2.5kΩ. So in this case, if the load has an impedance
less than 5kΩ, refresh will happen automatically at start up.
Positive supply rail. Bypass this pin to V
SS
with a capacitor
>1µF.
In applications where the bus voltage and chip
V
DD
are at the same potential, it is a good idea to run a separate line from the supply to each. This greatly
simplifies the filtering requirements.
12
V
DD
4
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
