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NM27C020VE120

产品描述OTP ROM, 256KX8, 120ns, CMOS, PQCC32, PLASTIC, LCC-32
产品类别存储    存储   
文件大小159KB,共14页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
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NM27C020VE120概述

OTP ROM, 256KX8, 120ns, CMOS, PQCC32, PLASTIC, LCC-32

NM27C020VE120规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Fairchild
零件包装代码QFJ
包装说明QCCJ, LDCC32,.5X.6
针数32
Reach Compliance Codeunknown
ECCN代码EAR99
最长访问时间120 ns
I/O 类型COMMON
JESD-30 代码R-PQCC-J32
JESD-609代码e0
长度13.995 mm
内存密度2097152 bit
内存集成电路类型OTP ROM
内存宽度8
功能数量1
端子数量32
字数262144 words
字数代码256000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织256KX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装等效代码LDCC32,.5X.6
封装形状RECTANGULAR
封装形式CHIP CARRIER
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
认证状态Not Qualified
座面最大高度3.56 mm
最大待机电流0.0001 A
最大压摆率0.03 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度11.455 mm

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NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM
NM27C020
July 1997
NM27C020
2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM
General Description
The NM27C020 is a high speed 2 Megabit CMOS UV-
EPROM manufactured on Fairchild’s advanced sub-micron
technology. Utilizing the AMG* architecture, this advanced
CMOS process delivers high speeds while consuming low
power.
The NM27C020 provides microprocessor-based systems
extensive storage capacity for large portions of operating
systems and application software. Its 80ns access time pro-
vides no-wait-state operation with high-performance CPUs.
The NM27C020 offers a single chip solution for the code
storage requirements of 100
firmware-based equipment. Frequently-used software rou-
tines are quickly executed from EPROM storage, greatly en-
hancing system utility.
The NM27C020 is manufactured using Fairchild’s advanced
CMOS AMG EPROM technology, and is one member of a
high density Fairchild EPROM series family which range in
densities up to 4Mb.
Features
n
High performance CMOS
— 80 ns access time
n
Simplified upgrade path
— V
PP
and PGM are “Don’t Care” during normal read
operation
n
Manufacturers identification code
n
JEDEC Standard Pin Configuration
— 32-pin DIP package
— 32-pin TSOP package
— 32-pin PLCC package
Block Diagram
DS010835-1
© 1997 Fairchild Semiconductor Corporation
DS010835
www.fairchildsemi.com
1
PrintDate=1997/08/27 PrintTime=12:38:12 9696 ds010835 Rev. No. 3
cmserv
Proof
1

 
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