1,048,576 W O R D S x 1 6 B I T
CMOS DYNAMIC RAM
GM71C16160C
GM71CS16160CL
Description
T h e G M 7 1 C ( S ) 1 6 1 6 0 C /C L i s t h e n e w
generation dynamic RAM organized 1,048,576
x 16 bit. GM71C(S)16160C/
CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71C(S)16160C/
CL offers
Fast Page Mode as a high speed access mode.
Multiplexed address inputs permit the
G M 7 1 C ( S ) 1 6 1 6 0 C /C L t o b e p a c k a g e d i n
standard 400 mil 42 pin plastic SOJ , and
standard 400mil 44(50)pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
F eatur es
*
*
*
*
1 ,048,576 Words x 16 Bit Organization
Fast Page Mode Capability
S ingle Power Supply (5V+/
-10%)
Fast Access Time & Cycle Time
(Unit: ns)
t
R A C
t
C A C
GM71C(S)16160C/ L-5
C
GM71C(S)16160C/ L-6
C
GM71C(S)16160C/ L-7
C
50
60
70
13
15
18
t
R C
90
110
130
t
P C
35
40
45
* Low Power
Active : 605/
550/ 9 5 m W ( M A X )
4
S tandby : 11mW (CMOS level : MAX )
0.83mW (L-version : MAX )
* R A S O nly Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
*
*
*
*
*
*
All inputs and outputs TTL Compatible
4096 Refresh Cycles/
64ms
4096 Refresh Cycles/
128ms (L-version)
Self Refresh Operation (L-version)
B attery B ack Up Operation (L-version)
2 CAS byte Control
P in Configur a t ion
4 2 SOJ
V
CC
I/ 0
O
I/ 1
O
I/ 2
O
I/ 3
O
V
CC
I/ 4
O
I/ 5
O
I/ 6
O
I/ 7
O
NC
NC
WE
RAS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
44(50) T S O P I I
V
SS
I/ 1 5
O
I/ 1 4
O
I/ 1 3
O
I/ 1 2
O
V
SS
I/ 1 1
O
I/ 1 0
O
I/ 9
O
I/ 8
O
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
NC
NC
WE
RAS
A11
A10
A0
A1
A2
A3
V
CC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
V
CC
I/ 0
O
I/ 1
O
I/ 2
O
I/ 3
O
V
CC
I/ 4
O
I/ 5
O
I/ 6
O
I/ 7
O
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
V
SS
I/ 1 5
O
I/ 1 4
O
I/ 1 3
O
I/ 1 2
O
V
SS
I/ 1 1
O
I/ 1 0
O
I/ 9
O
I/ 8
O
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
(Top View)
Rev 0.1 / Apr’
01
GM71C16160C
GM71CS16160CL
P in Descr iption
P in
F unction
Address Inputs
Refresh Address Inputs
Data Input/ Data Output
RAS
UCAS, LCAS
Row Address Strobe
Column Address Strobe
P in
WE
OE
CC
F unction
Read/ rite Enable
W
Output Enable
Power (+5V)
Ground
No Connection
V
SS
NC
O r d e r ing Infor m a t ion
T ype No.
GM71C(S)16160CJ/ LJ -5
C
GM71C(S)16160CJ/ LJ -6
C
GM71C(S)16160CJ/ LJ -7
C
Access Time
5 0 ns
60ns
70ns
Package
4 0 0 Mil
42 Pin
Plastic SOJ
GM71C(S)16160CT/ LT -5
C
GM71C(S)16160CT/ LT -6
C
GM71C(S)16160CT/ LT -7
C
5 0 ns
60ns
70ns
4 0 0 Mil
44(50) Pin
Plastic TSOP II
Absolute Maximum Ratings*
Symbol
Parameter
Ambient Temperature under B ias
S torage Temperature (Plastic)
Voltage on any Pin Relative to V
S S
Voltage on V
C C
Relative to V
S S
Short Circuit Output Current
Power Dissipation
Rating
0 ~
+
7 0
-55 ~
+
1 2 5
-1.0 ~
+
7 . 0 V
-1.0 ~
+
7 . 0 V
50
1.0
Unit
C
C
V
V
mA
W
T
A
T
STG
V
IN/O U T
V
CC
I
OUT
P
D
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Rev 0.1 / Apr’
01
GM71C16160C
GM71CS16160CL
R ecommended DC Operating Conditions
(T
A
= 0 ~
+
70C)
Symbol
Parameter
S upply Voltage
Input High Voltage
Input Low Voltage
M in
4.5
2.4
-1.0
T yp
5.0
-
-
Max
5.5
6.0
0.8
Unit
V
V
V
V
CC
V
IH
V
IL
Note: All voltage referred to V ss.
T he supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.
T r uth Table
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
H to L
H to L
H to L
L
L
LCAS
D
L
H
L
L
H
L
L
H
L
L
H
L
H
L
L
H
UCAS
D
H
L
L
H
L
L
H
L
L
H
L
L
L
H
L
H
WE
D
H
H
H
L
L
L
L
L
L
H to L
H to L
H to L
D
D
D
D
H
OE
D
L
L
L
D
D
D
H
H
H
L to H
L to H
L to H
D
D
D
D
H
Output
Open
Valid
Valid
Valid
Open
Open
Open
Undefined
Undefined
Undefined
Valid
Valid
Valid
Open
Open
Open
Open
Operation
S tandby
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Word
Word
Word
Word
C B R R e f resh
or
Self Refresh
(L-series)
RAS-only
Refresh cycle
Read-modify
-write cycle
Delayed Write
cycle
Early write cycle
Read cycle
Notes
1,3
1,3
1,2,3
1,2,3
1,3
1,3
1,3
1,3
L
L
Open
Read cycle
(Output disabled)
Notes: 1. H: High (inactive) L: Low(active) D: H or L
2.
t
W C S
>= 0ns Early write cycle
t
W C S
<= 0ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Rev 0.1 / Apr’
01
GM71C16160C
GM71CS16160CL
CC
= 5V+/
-10%, V ss
A
= 0 ~ 70C)
Max
V
CC
0.4
110
100
mA
1, 2
Symbol
Parameter
Output Level
Output "H" Level Voltage (I
O U T
= - 5 m A
)
Output Level
Output "L" Level Voltage (I
O U T
=
4.
2m A )
Operating Current
( R A S , U C A S o r L C A S C y c l i n g
:
t
R C
=
t
R C
min)
5 0 ns
ns
70
M in
2.4
0
Unit
V
V
Note
V
OH
V
OL
I
CC1
-
-
90
2
110
100
2
mA
I
CC2
S tandby Current (TTL)
Power Supply Standby Current
( R A S , U C A S , L C A S = V
I H
,
D
O U T
=
High-Z)
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(t
R C
= t
R C
min)
Fast Page Mode Current
Fast Page Mode
(
P C
= t
P C
min)
5 0 ns
ns
70
5 0 ns
ns
70
I
CC3
-
90
115
105
mA
I
CC4
-
-
-
95
1
150
110
mA
5
I
CC5
S tandby Current (CMOS)
Power Supply Standby Current
( R A S , U C A S o r L C A S > = V
C C
- 0 . 2 V , D
O U T
= High-Z)
CAS-before-RAS Refresh Current
(t
R C
= t
R C
min)
5 0 ns
ns
70
I
CC6
-
-
-
90
mA
(Standby with CBR Refresh)
( =31.3us
,
<=
0.3
OUT
=
500
uA
I
CC8
U
CAS, LCAS = V
-
mA
1
D
OUT
I
CC9
(RAS, UCAS or LCAS<=0.2V
OUT
=
-
-10
-10
300
10
10
uA
uA
uA
I
L(I)
I
L(O)
Input Leakage Current
Any Input (0V
<=
V
I N
<=
6 V )
Output Leakage Current
( D
O U T
is Disabled, 0V
<=
V
O U T
<=
6 V )
Note: 1. I
C C
depends on output load condition when the device is selected.
(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = V
I L
3. Address can be changed once or less while LCAS and UCAS = V
I H
.
5. L-version.
Rev 0.1 / Apr 01
GM71C16160C
GM71CS16160CL
C a p a c itance
( V
C C
= 5V+/
-10%, T
A
= 25C)
Symbol
Parameter
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/
Out)
M in
-
-
-
Max
5
7
7
Unit
pF
pF
pF
Note
1
1
1, 2
C
I1
C
I2
C
I/O
Note: 1. Capacitance measured with B oonton Meter or effective capacitance measuring method.
2 . U C A S a n d L C A S = V
I H
to disable D
O U T
.
A C C h a r a c t e r istics
( V
C C
= 5V+/
-10%, T
A
= 0 ~
+
70C, Vss = 0V, Note 1, 2, 3, 19)
Test Conditions
Input rise and fall times : 5 ns
Input timing reference levels : 0.8V , 2 . 4 V
Output timing reference levels : 0.4V, 2.4V
Output load : 2TTL gate + C
L
( 1 0 0 pF)
(Including scope and jig)
R ead, W r ite, Read-Modify-W r ite and Refr esh Cycles
(Common Parameters)
Symbol
Parameter
Random Read or Write Cycle Time
R A S Precharge Time
C A S Precharge Time
RAS Pulse Width
CAS Pulse Width
Row Address Set up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
CAS Hold Time
C A S t o R A S Precharge T i m e
O E t o D
I N
Delay Time
OE Delay Time from D
I N
CAS Delay Time from D
I N
T ransition Time (Rise and Fall)
GM71C(S)16160
C/CL-5
GM71C(S)16160 GM71C(S)16160
C/CL-6
C/CL-7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Min M a x
Min
110
40
10
60
15
0
10
0
10
20
15
15
60
5
15
0
0
3
Max
-
-
-
10,000
10,000
Min M a x
130
50
10
70
18
0
10
0
15
20
15
18
70
5
18
0
0
3
-
-
-
10,000
10,000
t
R C
t
R P
t
C P
t
R A S
t
C A S
t
A S R
t
R A H
t
A S C
t
C A H
t
R C D
t
R A D
t
R S H
t
C S H
t
C R P
t
O D D
t
D Z O
t
D Z C
t
T
90
30
7
50
13
0
7
0
7
17
12
13
50
5
13
0
0
3
-
-
-
10,000
10,000
25
-
-
-
-
45
30
-
-
-
-
-
-
50
-
-
-
-
45
30
-
-
-
-
-
-
50
-
-
-
-
52
35
-
-
-
-
-
-
50
22
22
4
5
23
6
7
7
8
Rev 0.1 / Apr’
01
嵌入式系统
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