Crystal or Differential to
Differential Clock Fanout Buffer
8T39S04A
Datasheet
Description
The 8T39S04A is a high-performance clock fanout buffer. The input
clock can be selected from two differential inputs or one crystal input.
The internal oscillator circuit is automatically disabled if the crystal
input is not selected. The crystal pin can be driven by a single-ended
clock. The selected signal is distributed to four differential outputs
which can be configured as LVPECL, LVDS or HSCL outputs. In
addition, an LVCMOS output is provided. All outputs can be disabled
into a high-impedance state. The device is designed for a signal
fanout of high-frequency, low phase-noise clock and data signal. The
outputs are at a defined level when inputs are open or tied to ground.
It is designed to operate from a 3.3V or 2.5V core power supply, and
either a 3.3V or 2.5V output operating supply.
Features
•
•
•
•
•
Two differential reference clock input pairs
Differential input pairs can accept the following input levels:
LVPECL, LVDS, HCSL, HSTL and Single-ended
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Maximum Output Frequency
LVPECL - 2GHz
LVDS
- 2GHz
HCSL
- 250MHz
LVCMOS - 250MHz
Two banks, each has two differential output pairs that can be
configured as LVPECL or LVDS or HCSL
One single-ended reference output with synchronous enable to
avoid clock glitch
Output skew: 80ps (maximum), Bank A and Bank B at the same
output level
Part-to-part skew: 200ps (typical), design target
Additive RMS phase jitter @ 156.25MHz, (12kHz - 20MHz):
34.7fs (typical), 3.3V/ 3.3V
Supply voltage modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
•
•
Block Diagram
PullDown
•
•
•
•
PullDown
•
•
Pin Assignment
nQB0
nQB1
18
V
DDOB
V
DDOB
GND
24
REFOUT
23
22
21
20
19
nc
nCLK1
CLK1
V
DD
REFOUT
V
DDOREF
OE_SE
SMODE1
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
GND
17
16
15
14
QB0
QB1
REF_SEL1
nCLK0
CLK0
REF_SEL0
XTAL_OUT
XTAL_IN
V
DD
SMODE0
8T39S04A
13
12
11
10
9
V
DDOA
V
DDOA
nQA0
32-pin, 5mm x 5mm VFQFN Package
©2019 Integrated Device Technology, Inc.
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nQA1
GND
GND
QA0
QA1
July 24, 2019
8T39S04A Datasheet
Pin Description and Pin Characteristic Table
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0
Name
GND
V
DDOA
QA0
nQA0
V
DDOA
QA1
nQA1
GND
SMODE0
V
DD
XTAL_IN
XTAL_OUT
REF_SEL0
CLK0
nCLK0
REF_SEL1
GND
nQB1
QB1
V
DDOB
nQB0
QB0
V
DDOB
GND
nc
nCLK1
CLK1
V
DD
REFOUT
V
DDOREF
OE_SE
SMODE1
ePAD
Power
Power
Output
Output
Power
Output
Output
Power
Input
Power
Input
Output
Input
Input
Input
Input
Power
Output
Output
Power
Output
Output
Power
Power
Unused
Input
Input
Power
Output
Power
Input
Input
Power
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Type
Description
Power supply ground.
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Power supply ground.
Output driver select for Bank A and Bank B outputs. See Table 3D for function.
LVCMOS/LVTTL interface levels.
Power supply pin.
Crystal oscillator interface.
Crystal oscillator interface.
Input clock selection. LVCMOS/LVTTL interface levels.
See
Table 3A
for function.
Non-inverting differential clock. Internally biased to 0.33V
DD.
Inverting differential clock. Internal resistor bias to 0.4V
DD
.
Input clock selection. LVCMOS/LVTTL interface levels.
See
Table 3A
for function.
Power supply ground.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QB outputs.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QB outputs.
Power supply ground.
No connect pin.
Inverting differential clock. Internal resistor bias to 0.4V
DD
.
Non-inverting differential clock. Internally biased to 0.33V
DD.
Power supply pin.
Single-ended reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REFOUT output.
Output enable. LVCMOS/LVTTL interface levels. See
Table 3B.
Output driver select for Bank A and Bank B outputs. See
Table 3D
for function.
LVCMOS/LVTTL interface levels.
Connect ePAD to ground to ensure proper heat dissipation.
NOTE:
Pulldown
and
Pullup
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
©2019 Integrated Device Technology, Inc.
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8T39S04A Datasheet
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input
Capacitance
OE_SE,
SMODE[1:0],
REF_SEL[1:0]
CLK0, CLK1
nCLK0, nCLK1
REFOUT
V
DDOREF
= 3.465V
V
DDOREF
= 2.625V
V
DDOREF
= 3.3V
V
DDOREF
= 2.5V
Test Conditions
Minimum
Typical
2
50
100
75
5.3
6.3
52
63
Maximum
Units
pF
k
k
k
pF
pF
Input Pulldown Resistor
Input Pullup
Resistor
Power
Dissipation
Capacitance
Output
Impedance
C
PD
R
OUT
REFOUT
©2019 Integrated Device Technology, Inc.
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8T39S04A Datasheet
Function Tables
Table 3A. REF_SELx Function Table
Control Input
REF_SEL[1:0]
00 (default)
01
10
11
Selected Input Reference Clock
CLK0, nCLK0
CLK1, nCLK1
XTAL
XTAL
Table 3B. OE_SE Function Table
OE_SE
0 (default)
1
REFOUT
High-Impedance
Enabled
NOTE: Synchronous output enable to avoid clock glitch.
Table 3C. Input/Output Operation Table, OE_SE
Input Status
OE_SE
0 (default)
1
REF_SEL [1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
1
00 (default)
CLK0 and nCLK0 are tied to ground
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
1
01
CLK1 and nCLK1 are tied to ground
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
REFOUT
High Impedance
Fanout Crystal Oscillator
Logic Low
Logic Low
Logic High
Logic Low
Logic Low
Logic Low
Logic High
Logic Low
Table 3D. Output Level Selection Table, QX[0:1], nQX[0:1]
SMODE1
0
0
1
1
NOTE: X denotes A and B.
SMODE0
0
1
0
1
Output Type
LVPECL (default)
LVDS
HCSL
High-Impedance
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8T39S04A Datasheet
Table 3E. Input/Output Operation Table, SMODE[1:0]
Input Status
SMODE[1:0]
11
00, 01 or 10
REF_SEL[1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
CLK0 and nCLK0 are tied to ground
00, 01 or 10
00 (default)
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
CLK1 and CLK1 are tied to ground.
00, 01 or 10
01
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
QA[1:0], nQA[1:0]
High Impedance
Fanout crystal oscillator
QA[1:0] = Low
nQA[1:0] = High
QA[1:0] = Low
nQA[1:0] = High
QA[1:0] = High
nQA[1:0] = Low
QA[1:0] = Low
nQA[1:0] = High
QA[1:0] = Low
nQA[1:0] = High
QA[1:0] = Low
nQA[1:0] = High
QA[1:0] = High
nQA[1:0] = Low
QA[1:0] = Low
nQA[1:0] = High
Table 3F. Input/Output Operation Table, SMODE[1:0]
Input Status
SMODE[1:0]
11
00, 01 or 10
REF_SEL[1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
CLK0 and nCLK0 are tied to ground
00, 01 or 10
00 (default)
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
CLK1 and nCLK1 are tied to ground
00, 01 or 10
01
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
QB[1:0], nQB[1:0]
High Impedance
Fanout Crystal Oscillator
QB[1:0] = Low
nQB[1:0] = High
QB[1:0] = Low
nQB[1:0] = High
QB[1:0] = High
nQB[1:0] = Low
QB[1:0] = Low
nQB[1:0] = High
QB[1:0] = Low
nQB[1:0] = High
QB[1:0] = Low
nQB[1:0] = High
QB[1:0] = High
nQB[1:0] = Low
QB[1:0] = Low
nQB[1:0] = High
©2019 Integrated Device Technology, Inc.
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July 24, 2019
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