Crystal or Differential-to-Differential
Clock Fanout Buffer
8T39S11A
Datasheet
Description
The 8T39S11A is a high-performance clock fanout buffer. The input
clock can be selected from two differential inputs or one crystal input.
The internal oscillator circuit is automatically disabled if the crystal
input is not selected. The crystal pin can be driven by a single-ended
clock.The selected signal is distributed to ten differential outputs
which can be configured as LVPECL, LVDS or HSCL outputs. In
addition, an LVCMOS output is provided. All outputs can be disabled
into a high-impedance state.
The device is designed for a signal fanout of high-frequency, low
phase-noise clock and data signal. The outputs are at a defined level
when inputs are open or tied to ground. It is designed to operate from
a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output
operating supply.
Features
•
•
•
•
Two differential reference clock input pairs
Differential input pairs can accept the following differential input
levels: LVPECL, LVDS, HCSL, HSTL or Single Ended
Crystal Input accepts 10MHz to 40MHz Crystal or Single Ended
Clock
Maximum Output Frequency
LVPECL - 2GHz
LVDS
- 2GHz
HCSL
- 250MHz
LVCMOS - 250MHz
Two banks, each has five differential output pairs that can be
configured as LVPECL or LVDS or HCSL
One single-ended reference output with synchronous enable to
avoid clock glitch
Output skew: 80ps (maximum)
(Bank A and Bank B at the same output level)
Part-to-part skew: 200ps (typical)
Additive RMS phase jitter @ 156.25MHz:
5.6fs RMS (10kHz - 1 MHz), typical @ 3.3V/ 3.3V
34.7fs RMS (12kHz - 20MHz), typical @ 3.3V/ 3.3V
Supply voltage modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
•
•
•
•
•
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•
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©2018 Integrated Device Technology, Inc.
1
November 29, 2018
8T39S11A Datasheet
Block Diagram
Pin Assignment for 7mm x 7mm 48-Lead VFQFN Package
nQB2
nQB3
nQB0
nQB1
V
DDOB
QB0
QB1
nQB4
24
23
22
21
20
V
DDOB
QB2
QB3
GND
nc
SMODEB1
nCLK1
CLK1
V
DD
GND
REFOUT
V
DDOREF
OE_SE
SMODEA1
GND
37
38
39
40
41
42
43
44
45
46
47
48
36 35 34 33 32 31 30 29 28 27 26 25
QB4
GND
SMODEB0
REF_SEL1
nCLK0
CLK0
REF_SEL0
GND
XTAL_OUT
XTAL_IN
V
DD
SMODEA0
GND
8T39S11A
19
18
17
16
15
14
1
2
3
4
5
6
7
8
9
10 11 12
13
V
DDOA
nQA0
nQA1
nQA2
V
DDOA
nQA3
©2018 Integrated Device Technology, Inc.
nQA4
QA0
QA1
QA2
QA3
QA4
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November 29, 2018
8T39S11A Datasheet
Pin Description and Pin Characteristic Tables
Table 1: Pin Descriptions
1
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
QA0
nQA0
QA1
nQA1
V
DDOA
QA2
nQA2
V
DDOA
QA3
nQA3
QA4
nQA4
GND
SMODEA0
V
DD
XTAL_IN
XTAL_OUT
GND
REF_SEL0
CLK0
nCLK0
REF_SEL1
SMODEB0
GND
nQB4
QB4
nQB3
QB3
V
DDOB
nQB2
QB2
V
DDOB
Output
Output
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Power
Input
Power
Input
Output
Power
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Power
Output
Output
Power
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Type
Description
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pins for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pins for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Power supply ground.
Output driver select for Bank A outputs. See
Table 8
for function.
LVCMOS/LVTTL interface levels.
Power supply pin.
Crystal oscillator interface.
Crystal oscillator interface.
Power supply ground.
Input clock selection. LVCMOS/LVTTL interface levels.
See
Table 3
for function.
Non-inverting differential clock. Internally biased to 0.33V
DD.
Inverting differential clock. Internally biased to 0.4V
DD.
Input clock selection. LVCMOS/LVTTL interface levels.
See
Table 3
for function.
Output driver select for Bank B outputs. See
Table 9
for function.
LVCMOS/LVTTL interface levels.
Power supply ground.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pins for Bank QB outputs.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pins for Bank QB outputs.
©2018 Integrated Device Technology, Inc.
3
November 29, 2018
8T39S11A Datasheet
Table 1: Pin Descriptions
1
(Continued)
Number
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
ePad
Name
nQB1
QB1
nQB0
QB0
GND
nc
SMODEB1
nCLK1
CLK1
V
DD
GND
REFOUT
V
DDOREF
OE_SE
SMODEA1
GND
GND
_EP
Output
Output
Output
Output
Power
Unused
Input
Input
Input
Power
Power
Output
Power
Input
Input
Power
Power
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Type
Description
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Power supply ground.
No connect pin.
Output driver select for Bank B outputs. See
Table 9
for function.
LVCMOS/LVTTL interface levels.
Inverting differential clock. Internally biased to 0.4V
DD.
Non-inverting differential clock. Internally biased to 0.33V
DD.
Power supply pin.
Power supply ground.
Single-ended reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REFOUT output.
Output enable. LVCMOS/LVTTL interface levels. See
Table 4.
Output driver select for Bank A outputs. See
Table 8
for function.
LVCMOS/LVTTL interface levels.
Power supply ground.
Connect ePad to ground to ensure proper heat dissipation.
NOTE 1.
Pulldown
and
Pullup
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
Table 2: Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input
Capacitance
OE_SE,
SMODEx[1:0],
REF_SEL[1:0]
CLK0, CLK1
nCLK0, nCLK1
REFOUT
REFOUT
REFOUT
REFOUT
V
DDOREF
= 3.465V
V
DDOREF
= 2.625V
V
DDOREF
= 3.3V
V
DDOREF
= 2.5V
Test Conditions
Minimum
Typical
2
50
100
75
5.3
6.3
52
63
Maximum
Units
pF
k
k
k
pF
pF
Input Pulldown Resistor
Input Pullup
Resistor
Power
Dissipation
Capacitance
Output
Impedance
C
PD
R
OUT
©2018 Integrated Device Technology, Inc.
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November 29, 2018
8T39S11A Datasheet
Function Tables
Table 3: REF_SELx Function Table
Control Input
REF_SEL[1:0]
00 (default)
01
10
11
Selected Input Reference Clock
CLK0, nCLK0
CLK1, nCLK1
XTAL
XTAL
Table 4: OE_SE Function Table
1
OE_SE
0 (default)
1
REFOUT
High-Impedance
Enabled
NOTE 1. Synchronous output enable to avoid clock glitch.
Table 5: Input/Output Operation Table, OE_SE
Input Status
OE_SE
0 (default)
1
REF_SEL [1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
1
00 (default)
CLK0 and nCLK0 are tied to ground
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
1
01
CLK1 and nCLK1 are tied to ground
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
REFOUT
High Impedance
Fanout crystal oscillator
Logic Low
Logic Low
Logic High
Logic Low
Logic Low
Logic Low
Logic High
Logic Low
Table 6: Input/Output Operation Table, SMODEA
Input Status
SMODEA[1:0]
11
00, 01 or 10
REF_SEL[1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
CLK0 and nCLK0 are tied to ground
00, 01 or 10
00 (default)
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
CLK1 and nCLK1 are tied to ground
00, 01 or 10
01
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
QA[4:0], nQA[4:0]
High Impedance
Fanout crystal oscillator
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = High
nQA[4:0] = Low
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = High
nQA[4:0] = Low
QA[4:0] = Low
nQA[4:0] = High
©2018 Integrated Device Technology, Inc.
5
November 29, 2018
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