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GAL6001
High Performance E
2
CMOS FPLA
Generic Array Logic™
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 30ns Maximum Propagation Delay
— 27MHz Maximum Frequency
— 12ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS
®
Advanced CMOS Technology
• LOW POWER CMOS
— 90mA Typical Icc
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL
®
and FPLA Devices
• APPLICATIONS INCLUDE:
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Functional Block Diagram
ICLK
INPUT
CLOCK
2
INPUTS
2-11
14
23
11
{
ILMC
RESET
IOLMC
AND
OUTPUT
ENABLE
14
D
E
23
OLMC
0
7
OR
D
BLMC
E
{
OUTPUTS
14 - 23
OCLK
OUTPUT
CLOCK
Macrocell Names
ILMC
BLMC
OLMC
INPUT LOGIC MACROCELL
BURIED LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
Pin Names
I
0
- I
10
ICLK
OCLK
INPUT
INPUT CLOCK
OUTPUT CLOCK
I/O/Q
V
CC
GND
BIDIRECTIONAL
POWER (+5)
GROUND
Description
Using a high performance E CMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24-
pin, 300-mil package.
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Advanced features that simplify programming and reduce test time,
coupled with E
2
CMOS reprogrammable cells, enable 100% AC, DC,
programmability, and functionality testing of each GAL6001 during
manufacture. As a result, Lattice Semiconductor delivers 100% field
programmability and functionality of all GAL products. In addition,
100 erase/write cycles and data retention in excess of 20 years are
specified.
2
Pin Configuration
PLCC
I/ICLK
I/ICLK
DIP
1
24
Vcc
I/O/Q
I/O/Q
I
I/O/Q
Vcc
NC
I/O/Q
I
I
I
25
I/O/Q
I/O/Q
I
4
I
I
I
NC
I
I
I
11
12
9
7
5
2
28
26
I
I
I
I
I
I
I
GND
12
6
GAL
6001
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
13
OCLK
GAL6001
Top View
14
16
23
I/O/Q
NC
21
I/O/Q
I/O/Q
19
18
I/O/Q
I
I
OCLK
GND
NC
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
6001_02
1
Specifications
GAL6001
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
GAL6001 Ordering Information
Commercial Grade Specifications
Tpd (ns)
30
Fmax (MHz)
27
Icc (mA)
150
150
Ordering #
GAL6001B-30LP
GAL6001B-30LJ
Package
24-Pin Plastic DIP
28-Lead PLCC
Part Number Description
XXXXXXXX _ XX
X
X X
GAL6001B
Device Name
Grade
Blank = Commercial
Speed (ns)
L = Low Power
Power
Package
P = Plastic DIP
J = PLCC
2
Specifications
GAL6001
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)
The GAL6001 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is configurable
as a block for asynchronous, latched, or registered inputs. Pin 1
(ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Configurable input blocks
provide system designers with unparalleled design flexibility. With
the GAL6001, external registers and latches are not necessary.
Both the ILMC and the IOLMC are block configurable. However,
the ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations are shown in the macrocell equivalent
diagrams on the following pages.
Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)
The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND ar-
ray, are available at the device pins. Cells in this group are known
as Output Logic Macrocells (OLMC).
The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinatorial, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the “D” XOR.
Polarity selection is available for BLMCs, since both the true and
complemented forms of their outputs are available in the AND array.
Polarity of all “E” sum terms is selected through the “E” XOR.
When the macrocell is configured as a D/E type register, it is clocked
from the common OCLK and the register clock enable input is con-
trolled by the associated “E” sum term. This configuration is useful
for building counters and state-machines with state hold functions.
When the macrocell is configured as a D-type register with a sum
term clock, the register is always enabled and its “E” sum term is
routed directly to the clock input. This permits asynchronous pro-
grammable clocking, selected on a register-by-register basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. Registers are reset
to a logic zero. If connected to an output pin, a logic one will oc-
cur because of the inverting output buffer.
There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer and always present). When the OLMC is used as an out-
put, the second feedback path is through the IOLMC. With this dual
feedback arrangement, the OLMC can be permanently buried (the
associated OLMC pin is an input), or dynamically buried with the
use of the output enable product term.
The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS-, JK-, and T-type registers with the same efficiency as a dedi-
cated RS-, JK-, or T-register.
The three macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.
3
Specifications
GAL6001
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
ILMC and IOLMC Configurations
ICLK
LATCH
E
Q
D
INVALID
REG.
INPUT
or I/O
10
MUX
0
0
1
1
0
1
10
Q
D
0
1
AND
ARRAY
LATCH
ISYN
ILMC/IOLMC
Generic Logic Block Diagram
ILMC (Input Logic Macrocell)
JEDEC Fuse Numbers
ISYN
8218
LATCH
8219
IOLMC (I/O Logic Macrocell)
JEDEC Fuse Numbers
ISYN
8220
LATCH
8221
4
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