PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
V850/SV1
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
TM
DESCRIPTION
The
µ
PD703039, 703039Y, 703040, 703040Y, 703041, and 703041Y (collectively known as the V850/SV1) are
products in the low-power series of V850 Family
TM
products, which are NEC’s single-chip microcontrollers for real-
time control.
The V850/SV1 employs the CPU core of the V850 Family, and has on-chip peripheral functions such as large
capacity ROM/RAM, a multi-function timer/counter, serial interface, A/D converter, DMA controller, PWM, and a
Vsync/Hsync separation circuit.
The V850/SV1 not only realizes the low power consumption necessary for applications such as camcorders, but
also extremely high cost performance.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SV1 User’s Manual Hardware
: U14462E
V850 Family User’s Manual Architecture : U10243E
FEATURES
{
Number of instructions: 74
{
Minimum instruction execution time:
62.5 ns (@ 16 MHz operation with main system clock)
{
General-purpose registers: 32 bits
×
32 registers
{
Instruction set (signed multiplication, saturation
operations, 32-bit shift instructions, bit manipulation
instructions, load/store instructions)
{
Memory space:
16 MB linear address space
Memory block allocation function: 2 MB per block
{
External bus: 16-bit multiplexed bus
{
Internal memory:
{
10-bit resolution A/D converter: 16 channels
{
Timer/counter
24-bit: 2 channels, 16-bit: 2 channels
8-bit: 8 channels
{
Watchdog timer: 1 channel
{
DMA controller: 6 channels
{
Interrupts and exceptions
Non-maskable interrupt: 2 sources
Maskable interrupt
:
µ
PD703039, 703040, 703041 (51 sources)
:
µ
PD703039Y, 703040Y, 703041Y (52 sources)
Software exception: 32 sources
Exception trap: 1 source
{
Serial interface (SIO)
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
3-wire variable length serial interface (CSI4)
I
2
C bus interface (I
2
C) (
µ
PD703039Y, 703040Y,
703041Y)
{
RTP: 8 bits
×
2 channels or 4 bits
×
4 channels
30.5
µ
s (@ 32.768 kHz operation with subsystem clock)
{
Watch timer: 1 channel
µ
PD703039, 703039Y
(ROM: 256 KB, RAM: 8 KB)
µ
PD703040, 703040Y
(ROM: 256 KB, RAM: 16 KB)
µ
PD703041, 703041Y
(ROM: 192 KB, RAM: 8 KB)
{
I/O lines Total: 151
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U13953EJ1V0DS00 (1st edition)
Date Published March 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
µ
PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
{
PWM output: 4 channels
{
Vsync/Hsync separation circuit
{
On-chip key return function
{
On-chip clock generator
{
Power saving function: HALT/IDLE/STOP modes
{
ROM correction: 4 points changeable
{
Package: 176-pin plastic LQFP (24
×
24 mm)
APPLICATIONS
{
System/servo/camera control of camcorders
{
Portable cameras such as digital still cameras
{
Cellular phones, portable information terminals, etc.
ORDERING INFORMATION
Part Number
Package
176-pin plastic LQFP (fine pitch) (24
×
24 mm)
176-pin plastic LQFP (fine pitch) (24
×
24 mm)
176-pin plastic LQFP (fine pitch) (24
×
24 mm)
176-pin plastic LQFP (fine pitch) (24
×
24 mm)
176-pin plastic LQFP (fine pitch) (24
×
24 mm)
176-pin plastic LQFP (fine pitch) (24
×
24 mm)
µ
PD703039GM-×××-UEU
µ
PD703039YGM-×××-UEU
µ
PD703040GM-×××-UEU
µ
PD703040YGM-×××-UEU
µ
PD703041GM-×××-UEU
µ
PD703041YGM-×××-UEU
Remark
×××
indicates ROM code suffix.
DIFFERENCES BETWEEN V850/SV1 PRODUCTS
Internal ROM
Internal RAM
8 KB
IC
None
Provided
16 KB
None
Provided
192 KB (mask ROM)
8 KB
None
Provided
256 KB (flash memory)
16 KB
None
Provided
Provided
2
V
PP
Pin
None
µ
PD703039
µ
PD703039Y
µ
PD703040
µ
PD703040Y
µ
PD703041
µ
PD703041Y
µ
PD70F3040
µ
PD70F3040Y
256 KB (mask ROM)
2
Preliminary Data Sheet U13953EJ1V0DS00
µ
PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
PIN CONFIGURATION
176-pin plastic LQFP (fine pitch) (24
×
24 mm)
µ
PD703039GM-×××-UEU
µ
PD703039YGM-×××-UEU
µ
PD703040GM-×××-UEU
µ
PD703040YGM-×××-UEU
µ
PD703041GM-×××-UEU
µ
PD703041YGM-×××-UEU
P12/SCK0/SCL0
Note 2
P13/SI1/RXD0
P14/SO1/TXD0
P15/SCK1/ASCK0
P20/SI2/SDA1
Note 2
P21/SO2
P22/SCK2/SCL1
Note 2
P23/SI3/RXD1
P24/SO3/TXD1
P25/SCK3/ASCK1
P26/TI2/TO2
P27/TI3/TO3
V
DD
V
SS
P30/TI000
P31/TI001
P32/TI010
P33/TI011
P34/TO0
P35/TO1
P36/TI4/TO4
P37/TI5/TO5
P120/SI4
P121/SO4
P122/SCK4
P123/CLO
P124/TI6/TO6
P125/TI7/TO7
P126/TI10/TO10
P127/TI11/TO11
P180
P181
P182
P183
P184
P185
P186
P187
V
DD
V
SS
P190
P191
P192
P193
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
P11/SO0
P10/SI0/SDA0
Note 2
P113
P112
P111
P110
WAIT
CLKOUT
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BV
SS
BV
DD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P96/HLDRQ
P95/HLDAK
P94/ASTB
P93/DSTB/RD
P92/R/W/WRH
P91/UBEN
P90/LBEN/WRL
V
SS
V
DD
AV
DD
AV
SS
AV
REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
P147
P146
P145/RTPTRG1
P144/TI9/INTTI9
P143/INTCP93
P142/INTCP92
P141/INTCP91
P140/INTCP90
P137/TO81
P136/TO80
P135/TCLR8/INTTCLR8
P134/TI8/INTTI8
P133/INTCP83
P132/INTCP82
P131/INTCP81
P130/INTCP80
V
SS
V
DD
P07/INTP6
P06/INTP5/RTPTRG0
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P157/RTP17
P156/RTP16
Notes 1.
Connect directly to V
SS.
2.
SCL0, SCL1, SDA0, and SDA1 are valid for the
µ
PD703039Y, 703040Y, and 703041Y only.
P194
P195
P196
P197
P170/KR0
P171/KR1
P172/KR2
P173/KR3
P174/KR4
P175/KR5
P176/KR6
P177/KR7
P160/PWM0
P161/PWM1
P162/PWM2
P163/PWM3
P164/CSYNCIN
P165/VSOUT
P166/HSOUT0
P167/HSOUT1
IC
Note 1
RESET
XT1
XT2
V
DD
X2
X1
V
SS
P100/RTP00
P101/RTP01
P102/RTP02
P103/RTP03
P104/RTP04
P105/RTP05
P106/RTP06
P107/RTP07
V
DD
V
SS
P150/RTP10
P151/RTP11
P152/RTP12
P153/RTP13
P154/RTP14
P155/RTP15
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Preliminary Data Sheet U13953EJ1V0DS00
3
µ
PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
PIN IDENTIFICATION
A16 to A21:
AD0 to AD15:
ADTRG:
ANI0 to ANI15:
ASCK0, ASCK1:
ASTB:
AV
DD
:
AV
REF
:
AV
SS
:
BV
DD
:
BV
SS
:
CLKOUT:
CLO:
CSYNCIN:
DSTB:
HLDAK:
HLDRQ:
IC:
INTCP90 to INTCP93,
INTP0 to INTP6,
INTTCLR8,
INTTI8, INTTI9
KR0 to KR7:
LBEN:
NMI:
P00 to P07:
P10 to P15:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P65:
P70 to P77:
P80 to P87:
P90 to P96:
P100 to P107:
Key Return
Lower Byte Enable
Non-Maskable Interrupt Request
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
Address Bus
Address/Data Bus
AD Trigger Input
Analog Input
Asynchronous Serial Clock
Address Strobe
Analog Power Supply
Analog Reference Voltage
Analog Ground
Bus Interface Power Supply
Bus Interface Ground
Clock Output
Clock Output (divided)
Csync Input
Data Strobe
Hold Acknowledge
Hold Request
Internally Connected
P110 to P113:
P120 to P127:
P130 to P137:
P140 to P147:
P150 to P157:
P160 to P167:
P170 to P177:
P180 to P187:
P190 to P197:
PWM0 to PWM3:
RD:
RESET:
RTP00 to RTP07,:
RTP10 to RTP17
RTPTRG0, RTPTRG1: RTP Trigger Input
R/W:
RXD0, RXD1:
SCK0 to SCK4:
SCL0, SCL1:
SDA0, SDA1:
SI0 to SI4:
SO0 to SO4:
TCLR8:
TI011, TI2 to TI11
TO0 to TO7, TO80,:
TO81, TO10, TO11
TXD0,TXD1:
UBEN:
V
DD
:
VSOUT:
V
SS
:
WAIT:
WRH:
WRL:
X1, X2:
XT1, XT2:
Transmit Data
Upper Byte Enable
Power Supply
Vsync Output
Ground
Wait
Write Strobe High Level Data
Write Strobe Low Level Data
Crystal for Main System Clock
Crystal for Subsystem Clock
Timer Output
Read/Write Status
Receive Data
Serial Clock
Serial Clock
Serial Data
Serial Input
Serial Output
Timer Clear
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
Port 19
Pulse Width Modulation
Read
Reset
Real-time Output Port
HSOUT0, HSOUT1: Hsync Output
INTCP80 to INTPC83,: Interrupt Request from Peripherals
TI000, TI001, TI010,: Timer Input
4
Preliminary Data Sheet U13953EJ1V0DS00
µ
PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
INTERNAL BLOCK DIAGRAM
NMI
INTP0 to INTP6
INTCP80 to INTCP83,
INTCP90 to INTCP93
INTTCLR8
INTTI8, INTTI9
TI000, TI001,
TI010, TI011
TO0, TO1
TO80, TO81
TI8, TI9
TCLR8
TI2/TO2, TI3/TO3
TI4/TO4, TI5/TO5
TI6/TO6, TI7/TO7
TI10/TO10, TI11/TO11
CSYNCIN
HSOUT0, HSOUT1,
VSOUT
SO0
SI0/SDA0
Note 3
SCK0/SCL0
Note 3
SO2
SI2/SDA1
Note 3
SCK2/SCL1
Note 3
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SI4
SCK4
KR0 to KR7
INTC
ROM
PC
CPU
ROM correction
Multiplier
16
×
16
→
32
BCU
ALU
Instruction
queue
HLDRQ
HLDAK
ASTB
DSTB/RD
R/W/WRH
UBEN
LBEN/WRL
WAIT
A16 to A21
AD0 to AD15
Note 1
Timer/counter
16-bit timers
: TM0, TM1
8-bit timers
: TM2 to TM7,
TM10, TM11
24-bit timers
: TM8, TM9
32-bit barrel
shifter
RAM
System
register
General registers
32 bits
×
32
Note 2
Vsync/Hsync
SIO
CSI0/I
2
C0
Note 4
Ports
CSI2/I
2
C1
Note 4
CSI1/UART0
CSI3/UART1
Variable
length CSI4
Key return function
DMAC: 6 ch
RTP
P190 to P197
P180 to P187
P170 to P177
P160 to P167
P150 to P157
P140 to P147
P130 to P137
P120 to P127
P110 to P113
P100 to P107
P90 to P96
P80 to P87
P70 to P77
P60 to P65
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P15
P00 to P07
A/D
converter
CG
AV
DD
AV
REF
AV
SS
ANI0 to ANI15
ADTRG
CLKOUT
CLO
X1
X2
XT1
XT2
RESET
Watch timer
Watchdog timer
RTP00 to RTP07,
RTP10 to RTP17
RTPTRG0,
RTPTRG1
V
DD
V
SS
BV
DD
BV
SS
IC
PWM0 to PWM3
PWM
Notes 1.
µ
PD703039, 703039Y, 703040, 703040Y: 256 KB
µ
PD703041, 703041Y: 192 KB
2.
µ
PD703039, 703039Y, 703041, 703041Y: 8 KB
µ
PD703040, 703040Y: 16 KB
3.
SDA0, SDA1, SCL0, and SCL1 are valid for the
µ
PD703039Y, 703040Y, and 703041Y only.
2
4.
The I C function is valid for the
µ
PD703039Y, 703040Y, and 703041Y only.
Preliminary Data Sheet U13953EJ1V0DS00
5
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
