CAT34C02
2 kb I
2
C EEPROM for DDR2
DIMM Serial Presence
Detect
Description
The CAT34C02 is a 2 kb Serial CMOS EEPROM, internally
organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits
each.
It features a 16−byte page write buffer and supports both the
Standard (100 kHz) as well as Fast (400 kHz) I
2
C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory) or by setting an internal Write Protect flag
via Software command (this protects the lower half of the memory).
In addition to Permanent Software Write Protection, the
CAT34C02 also features JEDEC compatible Reversible Software
Write Protection for DDR2 Serial Presence Detect (SPD)
applications operating over the 1.7 V to 3.6 V supply voltage range.
The CAT34C02 is fully backwards compatible with earlier
DDR1 SPD applications operating over the 1.7 V to 5.5 V supply
voltage range.
Features
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TSSOP−8
Y SUFFIX
CASE 948AL
TDFN−8
VP2 SUFFIX
CASE 511AK
UDFN−8
HU3 SUFFIX
CASE 517AX
UDFN−8 EP
HU4 SUFFIX
CASE 517AZ
•
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•
•
•
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•
•
Supports Standard and Fast I
2
C Protocol
1.7 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Software Write Protection for Lower 128 Bytes
Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
Low power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
V
CC
PIN CONFIGURATION
A
0
A
1
A
2
V
SS
1
V
CC
WP
SCL
SDA
TSSOP (Y), TDFN (VP2),
UDFN (HU3), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTION
Pin Name
A
0
, A
1
, A
2
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
CAT34C02
SDA
SDA
SCL
A
2
, A
1
, A
0
WP
WP
V
CC
V
SS
Figure 1. Functional Symbol
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
V
SS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
March, 2011
−
Rev. 17
1
Publication Order Number:
CAT34C02/D
CAT34C02
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Voltage on Pin A
0
with Respect to Ground
Rating
−45
to +130
−65
to +150
−0.5
to +6.5
−0.5
to +10.5
Unit
°C
°C
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Symbol
I
CC
I
SB
Parameter
Supply Current
Test Conditions
V
CC
< 3.6 V, f
SCL
= 100 kHz
V
CC
> 3.6 V, f
SCL
= 400 kHz
Standby Current
All I/O Pins at GND or V
CC
T
A
=
−40°C
to +85°C
V
CC
≤
3.3 V
T
A
=
−40°C
to +85°C
V
CC
> 3.3 V
I
L
V
IL
V
IH
V
OL
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
V
CC
> 2.5 V, I
OL
= 3 mA
V
CC
< 2.5 V, I
OL
= 1 mA
Pin at GND or V
CC
−0.5
0.7 x V
CC
Min
Max
1
2
1
3
2
0.3 x V
CC
V
CC
+ 0.5
0.4
0.2
mA
V
mA
Units
mA
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Symbol
C
IN
(Note 4)
I
WP
(Note 5)
Parameter
SDA I/O Pin Capacitance
Other Input Pins
WP Input Current
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.6 V
V
IN
< V
IH
, V
CC
= 1.7 V
V
IN
> V
IH
I
A
(Note 5)
Address Input Current
(A0, A1, A2)
Product Rev H
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.6 V
V
IN
< V
IH
, V
CC
= 1.7 V
V
IN
> V
IH
Conditions
V
IN
= 0 V, f = 1.0 MHz, V
CC
= 5.0 V
Max
8
6
130
120
80
2
50
35
25
2
mA
mA
Units
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is
relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To
conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current
source.
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2
CAT34C02
Table 5. A.C. CHARACTERISTICS
(V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to +85°C) (Note 6)
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 7)
t
F
(Note 7)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 7)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 7 & 8)
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data Hold Time
Data Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to SDA Data Out
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power−up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
4
4.7
3.5
100
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Parameter
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. THERMAL CHARACTERISTICS
(Air velocity = 0 m/s, 4 layers PCB) (Notes 9 and 10)
Part Number
CAT34C02Y
CAT34C02VP2
CAT34C02HU3
CAT34C02HU4
Package
TSSOP
TDFN
UDFN
UDFN
q
JA
64
92
101
101
q
JC
37
15
18
18
Units
°C/W
°C/W
°C/W
°C/W
9. T
J
= T
A
+ P
D
*
q
JA
, where: T
J
is the Junction Temperature, T
A
the Ambient Temperature, P
D
the Power dissipation.
Example: CAT34C02VP2, V
CC
= 3.0 V, I
CCmax
= 1 mA, T
A
= 85°C: T
J
= 85°C + 3 mW * 92°C/W = 85.276°C.
10. T
J
= T
C
+ P
D
*
q
JC
, where: T
C
is the Case Temperature, etc.
Table 7. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 V
CC
to 0.8 V
CC
≤
50 ns
0.3 V
CC
, 0.7 V
CC
0.5 V
CC
Current Source: I
OL
= 3 mA (V
CC
≥
2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
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CAT34C02
Power−On Reset (POR)
The CAT34C02 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
The CAT34C02 will power up into Standby mode after
V
CC
exceeds the POR trigger level and will power down into
Reset mode when V
CC
drops below the POR trigger level.
This bi−directional POR feature protects the device against
‘brown−out’ failure following a temporary loss of power.
Pin Description
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A
0
, A
1
and A
2
: The Address pins accept the device address.
These pins have on−chip pull−down resistors.
WP:
The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor.
Functional Description
The CAT34C02 supports the Inter−Integrated Circuit
2
C) Bus data transmission protocol, which defines a device
(I
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT34C02 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
the bus as determined by the device address inputs A
0
, A
1
,
and A
2
.
I
2
C Bus Protocol
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
Start
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
Stop
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when following a
Write command) or sends the Slave into standby mode
(when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 3 bits, A
2
, A
1
and A
0
, select one of 8 possible Slave
devices. The last bit, R/W, specifies whether a Read (1) or
Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9
th
clock cycle (Figure 4). The Slave will also
acknowledge the byte address and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9
th
clock cycle. If
the Master acknowledges the data, then the Slave continues
transmitting. The Master terminates the session by not
acknowledging the last data byte (NoACK) and by sending
a STOP to the Slave. Bus timing is illustrated in Figure 5.
SDA
SCL
START BIT
STOP BIT
Figure 2. Start/Stop Timing
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CAT34C02
1
0
1
0
A
2
A
1
A
0
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
BUS RELEASE DELAY
(RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ t
AA
)
ACK SETUP (≥ t
SU:DAT
)
Figure 4. Acknowledge Timing
t
F
t
LOW
SCL
t
SU:STA
SDA IN
t
AA
SDA OUT
t
HD:STA
t
HIGH
t
LOW
t
R
t
HD:DAT
t
SU:DAT
t
SU:STO
t
DH
t
BUF
Figure 5. Bus Timing
Write Operations
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, byte address and data to be written
(Figure 6). The Slave acknowledges all 3 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Page Write
The internal byte address counter is automatically
incremented after each data byte is loaded. If the Master
transmits more than 16 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
The CAT34C02 contains 256 bytes of data, arranged in 16
pages of 16 bytes each. A page is selected by the 4 most
significant bits of the address byte following the Slave
address, while the 4 least significant bits point to the byte
within the page. Up to 16 bytes can be written in one Write
cycle (Figure 8).
Acknowledge polling can be used to determine if the
CAT34C02 is busy writing or is ready to accept commands.
Polling is implemented by interrogating the device with a
‘Selective Read’ command (see READ OPERATIONS).
The CAT34C02 will not acknowledge the Slave address,
as long as internal Write is in progress.
Delivery State
The CAT34C02 is shipped ‘unprotected’, i.e. neither SWP
flag is set. The entire 2 kb memory is erased, i.e. all bytes are
FFh.
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