Supertex inc.
MD3872DB1
MD3872 Front-End Ultrasound Receiver Demoboard
Introduction
The MD3872 is a low power and low noise eight-channel
front-end receiver for medical ultrasound imaging. Its excel-
lent low power dynamic performance is especially suitable
for portable ultrasound applications. Each channel’s circuit is
composed of a 14dB/18dB low noise pre-amplifier (LNA), a
voltage-controlled attenuator (VCA or TGC), a programma-
ble gain amplifier (PGA), an anti-aliasing filter (AAF) and an
analog-to-digital (ADC) converter. The gain and gain range
of the VGA can be digitally configured separately. The gain
of the PGA can be set to one of four discrete values: 23.5dB,
29dB, 34.5dB or 40dB. The VCA can be continuously varied
by a control voltage from -47dB to a maximum of 0dB.
In CW mode, an integrated trans-conductance amplifier is
driven by the LNA to generate differential output current.
The resulting signal currents of each channel then connect
to an 8×8 differential cross-point switch which can be pro-
grammed through the SPI. The 12-bit ADC is based on a
pipeline structure to provide high static linearity. The data,
clock, and frame alignment signal outputs are serial LVDS in
binary format for each channel.
General Description
The MD3872DB1 provides a very useful platform to evaluate
this low power and low noise 12-bit resolution ADC ultrasound
front-end receiver. Simply connect a 5V power supply to the
board and a USB cable to your computer.
The on-board MD3872 and T/R switch ICs, TGC, DAC,
FPGA, de-serialized LVDS, clock generator, DDR2 data
memory, isolated USB interface, JTAG SPI connector,
RS232 serial interface and low noise DC/DC power supplies
make a stand alone, desktop 8-channel ultrasound receiver
data acquisition evaluation system.
The MD3872DB1 package includes the demoboard
power supply cable, USB cable, software driver and PC
user interface software files. All software files including
the EEPROM file, FPGA configuration file and PC user
interface software files are web downloadable for updating
if necessary.
This datasheet describes the detail of the built-in hardware
features and PC interface software installation and step by
step operation of the board..
Block Diagram
Doc.# DSDB-MD3872DB1
A051713
Supertex inc.
www.supertex.com
MD3872DB1
MD3872DB1 Hardware Design
The eight channels of MD3872 LNA inputs are connected
to eight input signal SMA connectors via a transmit/receive
switch circuit, TRSW, as shown below. The T/R switches
used here are two Supertex MD0105s, 4-channel, ±130V,
15Ω devices. They are two-terminal devices. A pair of back-
to-back diodes, D24, are present to protect the LNA input
circuit from high-voltage transmission pulses and voltage
spikes from the transducer and long cable lines. The T/R
switch provides a low on-resistance (normal ON state) at
receiving time and a high impedance (OFF state) when high
voltage pulses are present. These input circuits enable the
user to directly evaluate their echo signal processing using
the MD3872 front-end receiver in their ultrasound system.
The trans impedance LNA gain setting of resistor R
f1
(R125)
is 249Ω when LNA SW is OFF. Because the R
f2
(R124)
is 590Ω, that means when LNA SW is ON, the effective
resistance is R
f1
//R
f2
= 175Ω. See the MD3872 datasheet
for the LNA input impedance calculation and LNA SW SPI
control bits.
In order to simplify testing of the CW cross-point switch
current source outputs, one channel CW1± pins have been
connected to a tightly coupled, center-taped, wind-band RF
transformer T2 and to an SMA connector J21.
There is an SPI serially interfaced 12-bit precision DAC on
board for quick evaluation of the TGC function of MD3872.
It can generate 0 to 1.8V with 0.44mV step resolution. R45
and R34 form a simple DAC output voltage-divider file that
scales the TGC signal. The Gain-Scaling Control pin GSC
has been pulled up to 1.8V AVDD by R30, which means that
GSC is set to 50dB/V TGC gain on this demoboard. One
can easily install a proper value on the resistor R36 (open as
default) to reset the TGC gain. Note that the VGSC minimum
voltage is 1.44V, which sets the TGC gain to about 66dB/V.
Although there is a built-in ADC reference voltage source
in MD3872, for evaluating the external referencing option,
there is an additional on-board precision 1.024V reference
device, U9, which can work with the jumper J24 to select the
internal or external reference. When selecting the external
reference, the EXT jumper should be Hi.
The MD3872 reference pins’ top and bottom voltages of
the ADC are not only for testing the voltages, but also for
bypassing capacitors differentially (C135 & C146) as well
as common-mode to ground (C153 & C154). When the IC
is working at 40 or 50MSPS speeds, all eight channels of
the ADl need a very large peak current into or out of the
reference voltage pins. It is important to keep the ADC
reference filtered as the current ripples especially in the
differential mode.
Users should leave the EBC pin disconnected. It is for
manufacturer testing only. The AVDD pins are connected to
a low noise +1.8V isolated power supply. The AVDD supply
pins need to be thoroughly decoupled to make sure that LNA
is working a low EMI/RFI conditions.
All digital outputs, especially the eight channels of LVDS,
working at 480bit/s data speed consumes a large amount of
power. One can slightly increase the DVDD voltage by +1.90
to 1.95V for better LVDS output waveforms at 300MHz DCLK
when 50MSPS maximum sampling rate becomes necessary.
The DVDD power rail is supplied by a separate LDO U11.
These AVDD and DVDD regulators feedback sense pins are
directly connected to the ferrite bead down stream and the
corresponding power supply pins separately. This method
will provide accurate voltage and lower noise.
The MD3872 +3.3V CVDD it connected to a CW cross point
switch circuit. Foe those applications that do not need CW
signals, one can simply connect the CVDD to 1.8 as well.
PCB Board Design
The MD3872 sampling clock input signals are 40 or 50MHz
from two low-jitter LVDS crystal oscillators, via a shared
differential-clock bus, which is terminated with a 100Ω
differential load resistor. The bus lines must be comprised
of two closely coupled, length-matched, 50Ω impedances to
ground. The 100Ω resistor load must be placed very close to
the MD3872 CLK± pins.
Besides the clock input pins, all the other pairs of LVDS
output pins to FPGA de-serialized input pairs also need to
be the same type of transmission lines that are designed
on the PCB. The termination resistors, however, are not
needed due to the built-in LVDS termination feature of the
Spartan-6 FPGA circuit. But length-matching of the LVDS
lines is very critical to the ADC output data pairs OUTn± vs.
DCLK± and FCLK± pairs. Precision trace line impedance-
control by a PCB fabrication house is highly recommended,
although MD3872 has built-in programmable LVDS output
skew alignment features.
The most important thing about the PCB design for the
MD3872 receiver front-end IC, besides the line impedance
control, is the ground plane selection and ground integrity.
Supertex recommends that if MD3872 is on the top layer
of the PCB stack, then the ground must be the second
layer. The center-bottom of the IC’s thermal pad should be
well connected to the ground plane electrically as well as
thermally. The vias on the thermal pads should use about
a 0.3mm diameter drill for the through hole matrices with
1.0mm pitch. However, do not let the pad electrically con-
nect to the other layers of the PCB stack, even if they are
named as GND , but thermally it can connect to as many
Doc.# DSDB-MD3872DB1
A051713
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Supertex inc.
www.supertex.com
MD3872DB1
layers as possible to lower the thermal resistance of heat
sinking. The GND vias of all the decoupling capacitors of the
MD3872’s power supply pin should also connect to the sec-
ond layer with traces that are as short as possible, or even
without a trace. The GND plane should not have a split, long-
slot or large-hole. Make sure the top signal’s return currents
to ground freely select the best path, just like the top signal
path’s shadow-image is projected on to the GND plane for
minimizing its magnetic loop and therefore minimizing ERI/
RFI. PCB layout designers must make sure that no return
current paths are close to, crossing, or overlapping each
other on the ground plane. The power traces are normally
selected on the third layer for the power trace impedance
and de-coupling.
After correct configuration of the FPGA, a user interface win-
dow comes up, as shown in Fig. 2:
USB Driver Installation
The MD3872DB1 demoboard uses Spartan-6 FPGA as the
MD3782 LVDS de-serializer and data acquisition controller
interfaced to DDR memory and the USB controller. The USB
port on the CY7C68913A via is a 20Mbit/s USB isolator con-
nected to a PC USB port. To install the USB driver, plug the
USB cable into the PC, turn on the demoboard power sup-
ply, then install the driver by clicking the new USB device
and selecting the SupertexWinUsb.inf file which is provided
in the Supertex subdirectory of the demo software. After
installing the driver, you will see a new item under Control
Panel / Device Manager called “SupertexUsb / USB SAM-
PLE”. Click the “Supertex.exe” file to start running the demo
software.
Fig. 2
To acquire one of the 8-channels of MD3872 data, select
the “File/Acquire Data”. Select the desired “Sample Period”,
“Sample Point” and “Sample Channel” from the three op-
tions provided, then click the “Start button”.
Demoboard Software
Running the Supertex.exe file will automatically download the
FPGA “SuperTexFPGA.bin” file into the Spartan-6 FPGA first.
This procedure takes about 20 seconds. See figure below:
Fig. 3
A new time domain waveform window will come up, If the
input is a Sine wave, then the screen looks like this:
Fig. 1
Before running “SuperTex.exe”, some Windows XP or 7 us-
ers may need to install the “.net runtime library”. It can be
found in the “Driver” subdirectory in the “SuperTex” folder as
“dotNetfx.exe”.
Fig. 4
Supertex inc.
www.supertex.com
Doc.# DSDB-MD3872DB1
A051713
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MD3872DB1
To zoom in/out on the time or amplitude axis, use (Ctrl + /
-) or (Ctrl ] / [). Or use the “Horizontal Zoom” and “Vertical
Zoom” pull-down menus.
The frequency domain and harmonic analysis are available
by clicking the “Fourier Transform” Tab above the waveform
window. If an RF frequency peak top is not located at 0 dB
or where you want it be as the reference point, you could
simply use (Ctrl > / <) to offset the FFT results.
To save a data file of an acquisition resolution use “File/
Save As (*.spd) file for later review, or “Save to CSV” file for
Excel data base or MATLAB or MathCAD evaluation.
Controlling the TGC DAC
To control the TGC voltage which outputs from the SPI serial
interfaced DAC, select “File / TGC DAC Write” at the top level
screen of the demo software window,then use the default
Address Input value 3 and type any number within 000 to
FFF in Hex. That corresponds to abut 0 to 1.8V in voltage
at the TGC pin of MD3872, and corresponds to -47dB to
0dB for the TGC attenuations. The TGC linear-in-Log control
curve from 0 to 1.7V is shown below.
Fig. 5
Configuring the MD3872 SIP Register
Fig. 7
0
Using the demoboard software, you can easily configure the
MD3872 SPI register, by selecting the “MD3872 Cfg” menu.
The configuration window looks like this:
TGC Attenuation (dB)
Maximum Slope
Minimum Slope
-47
0
TGC Voltage (V)
1.7
Fig. 6
On the left side, a table of MD3872 SPI registers is shown in
binary. The ADDR column is in Hex 0 to F. The register data
field help table is on the right side. The help contents will pro-
gressively change as the selected ADDR row is changing.
After you enter the wanted number to the page, select the
“Save / to Hardware” or “Save / to (*.md) file for later recall.
Fig. 8
That means setting the TGC DAC to more than 0xF1C will
make all the channels have attenuation of about 0dB.
Doc.# DSDB-MD3872DB1
A051713
4
Supertex inc.
www.supertex.com
MD3872DB1
Low Power MD3872 Runs Cool
The low power dissipation feature of the MD3872 is supe-
rior to its competition. To the right is a IR thermal image of
the chip on the demoboard. It
show
s about 52°C at the sur-
face when 8-channels are running at 40MHz, with AVDD =
+1.80V, DVDD = +1.97V CVDD = +3.3V. The emissivity of
the package is about 0.95. This demoboard PCB stack is
8-layers and uses 0.5oz copper thickness
Demoboard Circuit Schematic
AVDD1V8
AVDD2
AVDD1V8
2
2
FB1
DVDD1V8
DVDD1
FB3
C63 C64 C65 C66
1.0 1n 1.0 1n
1
FB4
470uF 6.3V
C46
+
C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62
1.0 1n 1.0 1n 1.0 1n 1.0 1n 1.0 1n 1.0 1n 1.0 1n 1.0 1n
AVDD1V8
AVDD1
FB10
C69 C70
1.0 1n
C71 C72
1.0 1n
2
CVDD3V3
1
C28 C29
1.0 1n
1
2
2
470uF 6.3V
J5
R126
0
R127
2K
U20-1
C94
+
AVDD3
6
VDD
C120
1.0
C125 C126
1.0 1n
1
Rx Inputs
C95 C96 C97 C98 C99 C100C101C102C103C104C105C106C107C108C109C110
1.0 1n 1.0 1n 1.0 1n 1.0 1n 1.0 1n 1.0 1n 1.0 1n 1.0 1n
FB12
470uF 6.3V
C119
+
C26
10n
VDD3V3
1
C116 C117 C118
1n
1.0
1n
X1
ADC CLK 50MHz
FOX-LC735R-30
1
2
19
NCA NCB
A
B
GND
MD0105K6
18
17
AVDD1V8
1
2
MD_PDWN
MD_STBY
OSC_FRE2
EN
NC
OUT2
OUT1
5
4
LVDS_CLKN
LVDS_CLKP
2
FB15
C127 C128
1.0 1n
J6
R166
0
R167
2K
U20-2
3
4
20
NCA NCB
A
B
GND
MD0105K6
124
114
33
36
62
99
37
58
108
115
3
10
17
24
94
87
80
73
AVDD3
AVDD4
AVDD5
AVDD6
AVDD7
DVDD
DVDD
AVDD0
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
PDWN
STBY
CVDD
CVDD
100 R28
LVDS_CLKP
LVDS_CLKN
2
9
16
23
95
88
81
74
61
60
16
15
32
31
J7
R171
0
R172
2K
U20-3
CLK+
CLK-
DCLK+
DCLK-
FCLK+
FCLK-
OUT1+
OUT1-
49
48
47
46
57
56
MD_DCLKP
MD_DCLKN
MD_FCLKP
MD_FCLKN
MD_OUTP0
MD_OUTN0
5
6
21
NCA NCB
A
B
GND
MD0105K6
14
13
VDD3V3
C111
10n
3
GND
1
C123
1.0
C124
1n
TRSW1
XDRC
COM
TRSW2
J11
0
R177
2K
OSC_FRE1
MD0105K6
J13
R196
0
R197
2K
U21-1
TRSW4
COM
XDRC
COM
TRSW8
1
2
19
NCA NCB
A
B
GND
MD0105K6
18
17
PASW
PA-
LNA+
LNA-
PASW
PA-
LNA+
LNA-
PASW
PA-
LNA+
LNA-
PASW
PA-
LNA+
LNA-
PASW
PA-
LNA+
LNA-
93
92
91
89
4
5
6
8
11
12
13
15
18
19
20
22
25
26
27
29
126
125
100
101
102
103
104
105
106
107
116
117
118
119
120
121
122
123
SW4
PA4-
IN4+
IN4-
SW5
PA5-
IN5+
IN5-
SW6
PA6-
IN6+
IN6-
SW7
PA7-
IN7+
IN7-
SW8
PA8-
IN8+
IN8-
GSC
TGC
CW1+
CW1-
CW2+
CW2-
CW3+
CW3-
CW4+
CW4-
CW5+
CW5-
CW6+
CW6-
CW7+
CW7-
CW8+
CW8-
OUT4+
OUT4-
51
50
MD_OUTP3
MD_OUTN3
XDRC
COM
16
15
TRSW5
J15
0
R182
2K
NCA NCB
A
B
GND
MD0105K6
XDRC
COM
TRSW6
OUT6+
OUT6-
3
R47
0
VIN
R181
U21-2
3
4
20
MD3872
43
42
U9
2
U7
OUT5+
OUT5-
45
44
CVDD3V3
C157 C158
1.0
1n
R44
1K
MD_OUTP4
MD_OUTN4
3
NCA NCB
B
A
GND
COM
TRSW3
XDRC
PASW
PA-
LNA+
LNA-
86
85
84
82
SW3
PA3-
IN3+
IN3-
OUT3+
OUT3-
53
52
MD_OUTP2
MD_OUTN2
GND
R176
U20-4
XDRC
12
11
7
8
22
PASW
PA-
LNA+
LNA-
79
78
77
75
SW2
PA2-
IN2+
IN2-
OUT2+
OUT2-
55
54
1
MD_OUTP1
MD_OUTN1
VDD
PASW
PA-
LNA+
LNA-
72
71
70
68
SW1
PA1-
IN1+
IN1-
X2
ADC CLK 40MHz
FOX-LC735R-40
6
EN
NC
OUT2
OUT1
5
4
LVDS_CLKN
LVDS_CLKP
2
External VREF
LM4140
MD_OUTP5
MD_OUTN5
EN
NC
VREF
6
C161
1.0
VREF1V024
XDRC
COM
14
13
TRSW7
J17
R186
0
R187
2K
U21-3
5
6
21
NCA NCB
A
B
GND
MD0105K6
XDRC
AVDD1V8
MD_TGC
R31
50
COM
50
R30
OUT8+
OUT8-
39
38
MD_OUTP7
MD_OUTN7
J19
SMA
R191
0
R192
2K
U21-4
7
8
22
NCA NCB
A
B
GND
MD0105K6
12
11
R34
750
TP19
C131
0.01
INF R36
0.01
C132
SDI
SDO
SCLK
CSB
FLEX
EXT
EBC
NC
NC
NC
NC
64
34
63
65
98
110
128
66
59
35
67
MD_EXT
R39
INF
MD_SDI
MD_SDO
MD_SCLK
MD_CSB
MD_FLEX
DVDD1V8
R37
1K
CVDD3V3
C155 C156
1.0 1n
1
4
7
8
OUT7+
OUT7-
41
40
MD_OUTP6
MD_OUTN6
GND
GND
GND
GND
5
TGC DAC
3
2
1
TGC_SDI
TGC_SCK
TGC_CS_LD
U8
LTC2630-LM12-LCZB
TP20
1
2
3
J24
HEAD3
MD_TGC
R45
249
VCC
4
SDI
SCK
6
VOUT
GND
5
RBIAS
VREF
REF+
REF-
GND
GND
GND
GND
GND
CM0
CM1
CM2
CM3
CM4
CM5
CM6
CM7
CM8
CS-LD
DAC Output 0 to 2.5V
J21
CWD1
CVDD3V3
T2
MCL_T1-6T
CW1+
1
4
127
69
76
83
90
7
14
21
28
1
30
129
96
97
111
112
113
2
SMA
5
6
C159
0.1
CW1-
0.1 0.1 0.1 0.1 0.1
0.1 0.1 0.1 0.1
C139C140C141C142C143
C149C150C151C152
R43
INF
C144
1.0
C135
0.1
C145
3
C146
R41
4.7
49.9K
0.1 C153
C154
0.1
0.1
VREF1V024
TRSW
R179
590
PASW
R180
249
PA-
C364
C365
18nF
LNA+
XDRC
1
R183 D35
BAS40-04
2K
COM
2
0.01
C367
C366
22pF
109
LNA-
0.01
3
Doc.# DSDB-MD3872DB1
A051713
5
Supertex inc.
www.supertex.com
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