FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20865-3E
FLASH MEMORY
CMOS
2M (256K
×
8/128K
×
16) BIT
MBM29LV200TC
-70/-90/-12
/MBM29LV200BC
-70/-90/-12
s
FEATURES
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minimum 100,000 program/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
One 8K word, two 4K words, one 16K word, and three 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode
• Low V
CC
write inhibit
≤
2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
(Continued)
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MBM29LV200TC
-70/-90/-12
/MBM29LV200BC
-70/-90/-12
s
GENERAL DESCRIPTION
The MBM29LV200TC/BC are a 8M-bit, 3.0 V-only Flash memory organized as 256K bytes of 8 bits each or 128K
words of 16 bits each. The MBM29LV200TC/BC are offered in 48-pin TSOP(I) and 44-pin SOP packages. These
devices are designed to be programmed in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and
5.0 V V
CC
are not required for write or erase operations. The devices can also be reprogrammed in standard
EPROM programmers.
The standard MBM29LV200TC/BC offer access times 70 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29LV200TC/BC are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV200TC/BC are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV200TC/BC are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29LV200TC/BC memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
3
MBM29LV200TC
-70/-90/-12
/MBM29LV200BC
-70/-90/-12
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes
• Individual-sector, multiple-sector, or bulk-erase capability
• Individual or multiple-sector protection is user definable.
(×8)
16K byte
(×16)
64K byte
(×8)
(×16)
3FFFFH 1FFFFH
3BFFFH 1DFFFH
8K byte
39FFFH 1CFFFH
8K byte
37FFFH 1BFFFH
32K byte
2FFFFH 17FFFH
64K byte
1FFFFH 0FFFFH
64K byte
0FFFFH 07FFFH
64K byte
00000H 00000H
MBM29LV200TC Sector Architecture
16K byte
8K byte
8K byte
32K byte
64K byte
64K byte
3FFFFH 1FFFFH
2FFFFH 17FFFH
1FFFFH 0FFFFH
0FFFFH 07FFFH
07FFFH 03FFFH
05FFFH 02FFFH
03FFFH 01FFFH
00000H
00000H
MBM29LV200BC Sector Architecture
4