November 2004
®
AS7C332MNTD18A
3.3V 2M × 18 Pipelined SRAM with NTD
TM
Features
• Organization: 2,097,152 words × 18 bits
• NTD
™
architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.2/3.5/3.8 ns
• Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP and 165-ball BGA packages
• Byte write enables
Logic block diagram
A[20:0]
21
D
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
• Boundary Scan using IEEE 1149.1 JTAG function is
available in 165 Ball BGA Package only.
Address
register
Burst logic
Q
21
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
CLK
D
Q
21
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
2 M x 18
SRAM
Array
DQ[a,b]
18
D
Data
Q
Input
Register
CLK
18
18
18
18
CLK
CEN
CLK
OE
Output
Register
18
OE
DQ[a,b]
Selection guide
-200
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
11/25/04, V 1.5
-166
6
166
3.5
400
150
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
P. 1 of 26
5
200
3.2
450
170
90
Alliance Semiconductor
Copyright © Alliance Semiconductor. All rights reserved.
AS7C332MNTD18A
®
32 Mb Synchronous SRAM products list
1,2
Org
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
Part Number
AS7C332MPFS18A
AS7C331MPFS32A
AS7C331MPFS36A
AS7C332MPFD18A
AS7C331MPFD32A
AS7C331MPFD36A
AS7C332MFT18A
AS7C331MFT32A
AS7C331MFT36A
AS7C332MNTD18A
AS7C331MNTD32A
AS7C331MNTD36A
AS7C332MNTF18A
AS7C331MNTF32A
AS7C331MNTF36A
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
Speed
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
NTD
1
-PL
NTD-FT
:
:
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
Pipelined Burst Synchronous SRAM with NTD
TM
Flow-through Burst Synchronous SRAM with NTD
TM
1. NTD: No Turnaround Delay. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
11/25/04, V 1.5
Alliance Semiconductor
P. 2 of 26
AS7C332MNTD18A
®
Functional description
The AS7C332MNTD18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as
2,097,152 words × 18 bits and incorporates a LATE LATE Write.
This variation of the 32Mb synchronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced write operation
that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all
applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for
valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or
read-modify-write operations.
NTD
™
devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle
flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With
NTD
™
, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined
mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W
pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including
burst, can be stalled using the CEN=1, the clock enable input.
The AS7C332MNTD18A operates with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a separate power supply
(V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP and 165-ball BGA packages.
Capacitance
Parameter
Input capacitance
I/O capacitance
*
Guaranteed not tested
Symbol
C
IN*
C
I/O*
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
Min
-
-
Max
5
7
Unit
pF
pF
TQFP and BGA thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled
Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
4–layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
11/25/04, V 1.5
Alliance Semiconductor
P. 5 of 26
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
