INDEX
ADVANCED INFORMATION
MX29F040
4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY
FEATURES
• 524,288 x 8 only
• Single power supply operation
- 5.0V only operation for read, erase and program
operation
• Fast access time: 70/90/120ns
• Low power consumption
- 30mA maximum active current
- 1uA typical standby current
• Command register architecture
- Byte Programming (7us typical)
- Block Erase
8 equal blocks of 64K-Byte each
• Auto Erase (chip & block) and Auto Program
- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends an erase operation to read data from,
or program data to, another sector that is not being
erased, then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
• Sector protect/unprotect for 5V only system or 5V/
12V system.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit≤3.2V
• Package type:
- 32-pin PLCC, TSOP or PDIP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
GENERAL DESCRIPTION
The MX29F040 is a 4-mega bit Flash memory organized
as 512K bytes of 8 bits. MXIC's Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX29F040 is packaged
in 32-pin PLCC, TSOP, PDIP. It is designed to be
reprogrammed and erased in-system or in-standard
EPROM programmers.
The standard MX29F040 offers access times as fast as
70ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F040 has separate chip enable (CE) and output
enable (OE ) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F040 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and programming mechanisms. In addition,
the combination of advanced tunnel oxide
processing and low internal electric fields for erase
and programming operations produces reliable
cycling. The MX29F040 uses a 5.0V±10% VCC
supply to perform the High Reliability Erase and
auto Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to
100 milliamps on address and data pin from -1V to
VCC + 1V.
P/N:PM0538
REV. 0.8, AUG. 01, 1998
1
INDEX
MX29F040
PIN CONFIGURATIONS
32 PDIP
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
32 PLCC
VCC
A12
A15
A16
A18
A17
30
29
WE
A7
A6
A5
A4
A3
A2
A1
A0
Q0
5
4
1
32
A14
A13
A8
A9
MX29F040
9
MX29F040
25
A11
OE
A10
CE
13
14
Q1
Q2
GND
17
Q3
Q4
Q5
21
20
Q6
Q7
32 TSOP (Standard Type) (12mm x 20mm)
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
32 TSOP (Reverse Type) (12mm x 20mm)
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
MX29F040
MX29F040
PIN DESCRIPTION
SYMBOL
A0~A18
Q0~Q7
CE
WE
OE
GND
VCC
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Output Enable Input
Ground Pin
+5.0V single power supply
SECTOR STRUCTURE
MX29F040 SECTOR ADDRESS TABLE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A18
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
Address Range
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
Note:All sectors are 64 Kbytes in size.
P/N:PM0538
REV. 0.8, AUG. 01, 1998
2
INDEX
MX29F040
BLOCK DIAGRAM
WRITE
CE
OE
WE
CONTROL
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
PROGRAM/ERASE
STATE
X-DECODER
MX29F040
FLASH
ARRAY
ARRAY
STATE
REGISTER
ADDRESS
LATCH
A0-A18
AND
BUFFER
SENSE
AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
P/N:PM0538
REV. 0.8, AUG. 01, 1998
3
INDEX
MX29F040
AUTOMATIC PROGRAMMING
The MX29F040 is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm makes the external system do
not need to have time out sequence or to verify the data
programmed. The typical room temperature chip
programming time of the MX29F040 is less than 4
seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard
microprocessor write timings. The device will
automatically pre-program and verify the entire array.
Then the device automatically times the erase pulse
width, provides the erase verification, and counts the
number of sequences. A status bit toggling between
consecutive read cycles, provides feedback to the user
as to the status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches address and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality,
reliability, and cost effectiveness. The MX29F040
electrically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by
using the EPROM programming mechanism of hot
electron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register
to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 4 second. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
AUTOMATIC BLOCK ERASE
The MX29F040 is block(s) erasable using MXIC's
Auto Block Erase algorithm. Block erase modes
allow blocks of the array to be erased in one erase
cycle. The Automatic Block Erase algorithm
automatically programs the specified block(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (include 2
unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the program
verification, and counts the number of sequences. A
status bit similar to DATA polling and a status bit toggling
between consecutive read cycles, provides feedback to
the user as to the status of the programming operation.
P/N:PM0538
REV. 0.8, AUG. 01, 1998
4
INDEX
MX29F040
TABLE1. SOFTWARE COMMAND DEFINITIONS
First Bus
Command
Reset
Read
Read Silicon ID
Porgram
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Unlock for sector
protect/unprotect
Bus
Cycle
1
1
4
4
6
6
1
1
6
Cycle
Addr
XXXH
RA
555H
555H
555H
555H
XXXH
XXXH
555H
Data
F0H
RD
AAH
AAH
AAH
AAH
B0H
30H
AAH
2AAH 55H
555H
80H
555H AAH
2AAH 55H
555H 20H
2AAH 55H
2AAH 55H
2AAH 55H
2AAH 55H
555H
555H
555H
555H
90H
A0H
80H
80H
ADI
PA
DDI
PD
2AAH 55H
2AAH 55H
555H 10H
SA
30H
Second Bus
Cycle
Addr
Data
Third Bus
Cycle
Addr
Data
Fourth Bus
Cycle
Addr
Data
Fifth Bus
Cycle
Addr
Data
Sixth Bus
Cycle
Addr
Data
555H AAH
555H AAH
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, A4H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/
2AAH or 555H to Address A10~A0 in byte mode.
Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A18 in either state.
COMMAND DEFINITIONS
Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read
mode. Table 1 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Either of the two
reset command sequences will reset the device(when
applicable).
P/N:PM0538
REV. 0.8, AUG. 01, 1998
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
