DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD705101
V831
TM
32-BIT MICROPROCESSOR
DESCRIPTION
The
µ
PD70501 (V831) is a 32-bit RISC microprocessor for embedded control applications, with a high-performance
32-bit V830
TM
processor core and many peripheral functions such as a DRAM/ROM controller, 4-channel DMA
controller, real-time pulse unit, serial interface, and interrupt controller.
In addition to high interrupt response speed and optimized pipeline structure, the V831 offers sum-of-products
operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia
functions, and therefore, can provide high performance in multimedia systems such as internet/intra-net systems, car
navigation systems, high-performance televisions, and color FAXes.
Detailed explanations of the functions, etc. are given in the following user’s manuals. Be sure to read the
manuals before designing your systems.
V831 User’s Manual -Handware
: U12273E
V830 Family
TM
User’s Manual -Architecture : U12496E
FEATURES
• CPU function
• V830-compatible instructions
• Instruction cache
• Instruction RAM
• Data cache
• Data RAM
• Minimum number of instruction
execution cycles
• Number of general purpose
registers
• Memory space and I/O space
• Interrupt/exception function
• Non-maskable : External input : 1
• Maskable
: External input : 8 (of which 4 are
multiplexed with internal sources)
Internal source: 11 types
•
•
•
Bus control function
Wait control function
Memory access control function
: 32 bits
×
32
: 4 GB each
: 1 cycle
: 4 KB
: 4 KB
: 4 KB
: 4 KB
•
•
DMA controller
: 4 channel
Serial interface function
• Asynchronous serial interface (UART): 1 channel
• Clocked serial interface (CSI)
: 1 channel
• Dedicated baud rate generator (BRG) : 1 channel
•
Timer/counter function
• 16-bit timer/event counter : 1 channel
• 16-bit interval timer
: 1 channel
: 3 I/O ports
: HALT and STOP modes
•
•
•
•
Port function
Standby function
Debug function
Clock generation function : PLL clock synthesizer
• Debug-dedicated synchronous serial
interface
• Trace-dedicated interface
: 1 channel
: 1 channel
The information in this document is subject to change without notice.
Document No. U12979EJ1V0DS00 (1st edition)
Date Published January 1998 N
Printed in Japan
©
1998
µ
PD705101
ORDERING INFORMATION
Part Number
Package
160-pin plastic LQFP (fine pitch) (24
×
24 mm)
µ
PD705101GM-100-8ED
PIN CONFIGURATION (TOP VIEW)
•
160-pin plastic LQFP (fine pitch) (24
×
24 mm)
µ
PD705101GM-100-8ED
GND
D2
D3
D4
D5
D6
D7
D8
V
DD
GND
D9
D10
D11
V
DD
GND
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
V
DD
GND
D22
D23
D24
V
DD
GND
D25
D26
D27
D28
D29
D30
D31
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
V
DD
D1
D0
LLCAS
LUCAS
ULCAS
UUCAS
RAS
OE
WE
A1
GND
V
DD
GND
V
DD
A2
A3
A4
A5
A6
A7
A8
A9
GND
V
DD
A10
A11
GND
V
DD
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
GND
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
V
DD
CLKOUT
TRCDATA0
TRCDATA1
TRCDATA2
TRCDATA3
DDI
DCK
DMS
DDO
A22
A23
GND
V
DD
IOWR
IORD
BCYST
READY
HLDRQ
HLDAK
CS1
CS2
GND
V
DD
CS3
CS4
CS5
GND
V
DD
CS6
CS7
INTP10/TO10
INTP12/TO11
INTP11
INTP13
TI
TCLR
INTP00
INTP01
GND
2
GND
LLMWR
LUMWR
ULMWR
UUMWR
MRD
TXD
RXD
GND
V
DD
PORT2/SI
PORT1/SO
PORT0/SCLK
V
DD
_PLL
X1
X2
GND_PLL
GND
V
DD
GND
V
DD
RESET
DRST
NMI
BT16B
GND
V
DD
GND
DMAAK0
DMAAK1
DMAAK2
DMAAK3
DMARQ0
DMARQ1
DMARQ2
DMARQ3
TC/REFRQ
INTP03
INTP02
V
DD
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
µ
PD705101
PIN NAMES
A1-A23
BCYST
BT16B
CLKOUT
CS1-CS7
D0-D31
DCK
DDI
DDO
: Address Bus
: Bus Cycle Start
: Boot Bus Size 16 bit
: Clock Out
: Chip Select
: Data Bus
: Debug Clock
: Debug Data Input
: Debug Data Output
NMI
OE
PORT0-PORT2
RAS
READY
REFRQ
RESET
RXD
SCLK
SI
SO
TC
TCLR
TI
TO10, TO11
: Non-Maskable Interrupt Request
: Output Enable
: Port
: Row Address Strobe
: Ready
: Refresh Request
: Reset
: Receive Data
: Serial Clock
: Serial Input
: Serial Output
: Terminal Count
: Timer Clear
: Timer Input
: Timer Output
: Trace Data
DMAAK0-DMAAK3 : DMA Acknowledge
DMARQ0-DMARQ3: DMA Request
DMS
DRST
GND
GND_PLL
HLDAK
HLDRQ
: Debug Mode Select
: Debug Reset
: Ground
: PLL Ground
: Hold Acknowledge
: Hold Request
TRCDATA0-TRCDATA3
TXD
ULCAS
ULMWR
UUCAS
UUMWR
V
DD
V
DD
_PLL
WE
X1, X2
: Transmit Data
: Upper Lower Column Address Strobe
: Upper Lower Memory Write
: Upper Upper Column Address Strobe
: Upper Upper Memory Write
: Power Supply
: PLL Power Supply
: Write Enable
: Crystal Oscillator
INTP00-INTP03, INTP10-INTP13
: Interrupt Request
From Peripheral
IORD
IOWR
LLCAS
LLMWR
LUCAS
LUMWR
MRD
: I/O Read
: I/O Write
: Lower Lower Column Address Strobe
: Lower Lower Memory Write
: Lower Upper Column Address Strobe
: Lower Upper Memory Write
: Memory Read
3
µ
PD705101
BLOCK DIAGRAM
DCK
DMS
DDI
DDO
TRCDATA0 - TRCDATA3
IOWR
IORD
DCU
UUMWR, ULMWR, LUMWR, LLMWR
MRD
READY
BT16B
CG
BCU
BCYST
CS1-CS7
A1-A23
SYU
V830 core
D0-D31
HLDRQ
DRST
X1
X2
CLKOUT
RESET
NMI
TI, TCLR
INTP10/TO10,
INTP12/TO11
RPU
HLDAK
RAS
UUCAS, ULCAS, LUCAS, LLCAS
INTP11, INTP13
INTP00 - INTP03
ICU
WE
OE
REFRQ/TC
P10
PORT0/SCLK
PORT1/SO
PORT2/SI
TXD
RXD
CSI
BRG
UART
DMAC
DMARQ0 - DMARQ3
DMAAK0 - DMAAK3
4
µ
PD705101
CONTENTS
1.
2.
3.
4.
5.
6.
7.
PIN FUNCTIONS LIST ......................................................................................................................... 6
INTERNAL UNITS ................................................................................................................................ 8
CPU FUNCTION ................................................................................................................................. 10
INTERRUPT/EXCEPTION PROCESSING FUNCTION ..................................................................... 11
BUS CONTROL FUNCTION .............................................................................................................. 13
WAIT CONTROL FUNCTION ............................................................................................................. 13
MEMORY ACCESS CONTROL FUNCTION ...................................................................................... 14
7.1
7.2
DRAM Control Function ............................................................................................................................ 14
Page-ROM Control Function ..................................................................................................................... 15
8.
9.
DMA FUNCTION ................................................................................................................................ 16
SERIAL INTERFACE FUNCTION ...................................................................................................... 18
9.1
9.2
9.3
Asynchronous Serial Interface (UART) ................................................................................................... 18
Clocked Serial Interface (CSI) ................................................................................................................... 20
Baud Rate Generator (BRG) ...................................................................................................................... 21
9.3.1 Configuration and function ................................................................................................................ 21
10. TIMER/COUNTER FUNCTION .......................................................................................................... 22
11. PORT FUNCTION .............................................................................................................................. 25
12. CLOCK GENERATION FUNCTION ................................................................................................... 27
13. STANDBY FUNCTION ........................................................................................................................ 28
14. RESET/NMI CONTROL FUNCTION .................................................................................................. 30
15. INSTRUCTIONS ................................................................................................................................. 31
15.1 Instruction Format ..................................................................................................................................... 31
15.2 Instructions (Listed Alphabetically) ......................................................................................................... 33
16. ELECTRICAL SPECIFICATIONS ...................................................................................................... 43
17. PACKAGE DRAWINGS ...................................................................................................................... 65
18. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 66
5
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