WB1336T
Dual Serial Input PLL with 2.0 and 1.1 GHz Prescalers
Features
• IC WORKS BiCMOS process
• Operating voltage 2.7V to 5.5V
• Operating frequency to 2.0GHz on PLL1 and 1.1 GHz on
PLL2 with inputs of –15dBm and V
CC
of 3.0V
• Lock detect feature
• Power-down mode I
CC
< 1µA typical at 3.0V
• Serial data input accepts data clock rates as low as 1KHz
• Low power/voltage operation with low current standby
mode
• On chip reference oscillator
• Available in a 20-pin TSSOP
(Thin Shrink Small Outline Package)
each with pulse swallow capability are included. The device
operates from 2.7V and dissipates only 38mW.
Figure 1
Pin Diagram
V
CC
1
V
P
1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
OSC_OUT
F
O
/LD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
2
V
P
2
D
O
PLL2
GND
F
IN
2
F
IN
2#
GND
LE
DATA
CLOCK
Applications
The IC WORKS WB1336T is a dual serial input PLL fre-
quency synthesizer designed for high performance dual con-
version TV, VCR, and Set-top tuner sections, as well as
downstream receivers for cable modems. The WB1336T is
also well suited for high volume, low cost wireless communi-
cations applications. One 2.0GHz and 1.1GHz prescaler,
Table 1
WB1336T
Order Information: WB1336TX-TR
Package
X = TSSOP
(0.173" Wide)
TR
Tape & Reel
Option
Part Number
Note:
Operating temperature range: –40°C to +85°C.
Figure 2 Dual PLL Block Diagram
GND (4)
(5)
F
IN
1
(6)
F
IN
1#
GND (7)
(1)
V
CC
V
CC
(20)
VP1 (2)
(3)
D
O
PLL1
Prescaler
64/65 or
128/129
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
fp1
Phase
Detector
Charge
Pump
(8)
OSC_IN
OSC_OUT
(9)
(13)
LE
(12)
DATA
(11)
CLOCK
Latch
Selector
19-Bit
Latch
Pwr-dwn
PLL1
fr1
fr fp
Monitor
Output
Selector
15-Bit
Reference Counter
20-Bit Latch
20-Bit Latch
Cntrl 22-Bit
Shift
Reg.
15-Bit
Reference Counter
19-Bit
Latch
Pwr-dwn
PLL2
(10)
F
O
/LD
fr2
Power
Control
(16)
F
IN
2
(15)
F
IN
2#
Prescaler
64/65 or
128/129
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Phase
Detector
fp2
Charge
Pump
(18)
D
O
PLL2
(14) GND
GND (17)
VP2 (19)
August 1999
Revision 1.2
IC WORKS DOCUMENT CONTROL : FDS-011 : REV 1
IC WORKS · 101 Nicholson Lane · San Jose, CA 95134-1359 · (408) 922-0202
Page 1 of 10
WB1336T
Figure 3 Application Diagram Example - WB1336T 2.0/1.1GHz Dual Hi/Hi PLL
V
P
1
10µF
V
CC
2.7-5.5V
10µF
10µF
V
P
2
0.1µF
0.1µF
100pF
0.1µF
(1)
V
CC
1
100pF
(20)
V
CC
2
100pF
0.1µF
0.1µF
(2)
V
P
1
100pF
(19)
V
P
2
100pF
0.1µF
100pF
2.0
GHz
VCO
22KΩ
3.3KΩ
68pF
0.01µF
0.001µF
(3)
D
O
PLL1
D
O
PLL2
(18)
3.3KΩ
22KΩ
1.1
GHz
VCO
(4)
GND
GND
(17)
0.001µF
0.1µF
68pF
18Ω
18Ω
1000pF
(5)
F
IN
1
F
IN
2
(16)
1000pF
18Ω
18Ω
18Ω
51Ω
51Ω
18Ω
(6)
RF LO
100pF
(15)
F
IN
1#
F
IN
2#
100pF
IF LO
(7)
GND
GND
(14)
(8)
OSC_IN
LE
(13)
2KΩ
3KΩ
(9)
OSC_OUT
DATA
(12)
2KΩ
3KΩ
(10)
F
O
/LD
CLOCK
(11)
2KΩ
3KΩ
Dual Serial Input PLL with 2.0 and 1.1 GHz Prescalers
IC WORKS DOCUMENT CONTORL : FDS-011 : REV 1
Revision 1.2
Page 2 of 10
WB1336T
Pin Definitions
Pin Name
V
CC
1
VP1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
OSC_OUT
F
O
/LD
Pin
No.
1
2
3
4
5
6
7
8
9
10
Pin
Type
P
P
O
G
I
I
G
I
O
O
Pin Description
Power Supply Connections for PLL1 and PLL2:
When power is removed from both the
Vcc1 and Vcc2 pins, all latched data is lost.
PLL1 Charge Pump Rail Voltage:
This voltage accommodates VCO circuits with tuning
voltages higher than the V
CC
of PLL1.
PLL1 Charge Pump Output:
The phase detector gain is I
P
/2π. Sense polarity can be
reversed by setting the FC bit in software (via the Shift Register).
Analog and Digital Ground Connections:
This pin must be grounded.
Input to PLL1 Prescaler:
Maximum frequency 2.0GHz.
Complementary Input to PLL1 Prescaler:
A bypass capacitor should be placed as closely
as possible to this pin and must be connected directly to the ground plane.
Analog and Digital Ground Connections:
These pins must be grounded.
Oscillator Input:
This input has a V
CC
/2 threshold and CMOS logic level sensitivity.
Oscillator Output
Lock Detect Pin:
The output is high when the loop is locked. It is multiplexed to the output of
the programmable counters or reference dividers in the test program mode.
(Refer to Table 4 for configuration)
Data Clock Input:
On the rising edge, one bit of data is loaded into the Shift Register.
Serial Data Input
Load Enable:
On the rising edge of this signal, the data stored in the Shift Register is
latched into the counters and configuration controls, PLL1 or PLL2 depending on the control
bit states.
Analog and Digital Ground Connections:
This pin must be grounded.
Complementary Input to PLL2 Prescaler:
A bypass capacitor should be placed as closely
as possible to this pin and must be connected directly to the ground plane.
Input to PLL2 Prescaler:
Maximum frequency 1.1GHz.
Analog and Digital Ground Connections:
These pins must be grounded.
PLL2 Charge Pump Output:
The phase detector gain is I
P
/2π. Sense polarity can be
reversed by setting the FC bit in software (via the Shift Register).
PLL2 Charge Pump Rail Voltage:
This voltage accommodates VCO circuits with tuning
voltages higher than the V
CC
of PLL2.
Power Supply Connections for PLL1 and PLL2:
When power is removed from both the
Vcc1 and Vcc2 pins, all latched data is lost.
CLOCK
DATA
LE
11
12
13
I
I
I
GND
F
IN
2#
F
IN
2
GND
D
O
PLL2
V
P
2
V
CC
2
14
15
16
17
18
19
20
G
I
I
G
O
P
P
Note:
Never have both PLLs programmed to the same frequency. They will lock to each other under these conditions. The
divide ration can be calculated using the following equation:
fvco = {(P * B) + A} * fosc / R where (A < B)
fvco: Output frequency of the external VCO.
fosc: The crystal reference oscillator frequency.
A: Preset divide ratio of the 7-bit swallow counter (0 to 127).
B: Preset ratio of the 11-bit programmable counter (3 to 2047).
P: Preset divide ratio of the dual modulus prescaler (64/65 or 128/129).
R: Preset ratio of the 15-bit programmable reference counter (3 to 32767).
The divide ratio N = (P * B) + A.
Dual Serial Input PLL with 2.0 and 1.1 GHz Prescalers
IC WORKS DOCUMENT CONTROL : FDS-011 : REV 1
Revision 1.2
Page 3 of 10
WB1336T
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other con-
Symbol
V
CC
or V
P
V
OUT
I
OUT
T
L
T
STG
Parameter
Power Supply Voltage
Output Voltage
Output Current
Lead Temperature
Storage Temperature
ditions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–0.5 to + 6.5
–0.5 to V
CC
+0.5
±15
+260
–55 to +150
Unit
V
V
mA
°C
°C
Handling Precautions
Devices should be transported and stored in antistatic con-
tainers.
These devices are static sensitive. Ensure that equipment
and personnel contacting the devices are properly grounded.
Cover workbenches with grounded conductive mats.
Always turn off power before adding or removing devices
from system.
Protect leads with a conductive sheet when handling or trans-
porting PC boards with devices.
If devices are removed from the moisture protective bags for
more than 36 hours, they should be baked at 85°C in a mois-
ture free environment for 24 hours prior to assembly in less
than 24 hours.
Recommended Operating Conditions
Symbol
V
CC
V
P
T
A
Parameter
Power Supply Voltage
Charge Pump Voltage
Operating Temperature
Rating
2.7 to 5.5
V
CC
to + 5.5
–40 to +85
Unit
V
V
°C
Ambient air at 0 CFM flow
Test Condition
Dual Serial Input PLL with 2.0 and 1.1 GHz Prescalers
IC WORKS DOCUMENT CONTORL : FDS-011 : REV 1
Revision 1.2
Page 4 of 10
WB1336T
Electrical Characteristics:
V
CC
= V
P
= 5V, T
A
=
–40°C
to +85°C Unless otherwise specified
Symbol
I
CC
I
PD
F
IN
1
F
IN
2
F
OSC
Fφ
V
IN
Oscillator Input Fre-
quency
Maximum Phase Detector
Frequency
Input Sensitivity
F
IN
1 and
F
IN
2
Parameter
Power Supply Current
PLL1 + PLL2
Power-down Current
Operating Frequency
Pin
V
CC
1,
V
CC
2
V
CC
1,
V
CC
2
F
IN
1
F
IN
2
OSC_IN
100
100
2
2
10
-15
-10
0.5
±50
DATA,
CLOCK,
LE
V
CC
* 0.8
V
CC
* 0.2
–10
F
O
/LD
V
CC
* 0.8
V
CC
* 0.2
D
O
PLL1
D
O
PLL2
-4.3
-1.25
4.3
1.25
3
0.05
10
4
4
Min
Typ
15
Max
Unit
mA
Test Condition
1
25
2000
1100
25
40
µA
MHz
MHz
MHz
MHz
MHz
dBm
dBm
V
P–P
µA
V
V
µA
V
V
mA
mA
mA
mA
%
Power-down, V
CC
= 3.0V
PLL1
PLL2
with OSC_OUT loaded
with OSC_OUT unloaded
V
CC
= 3.0V
V
CC
= 5.0V
V
OSC
I
IH
, I
IL
V
IH
V
IL
I
IH
, I
IL
V
OH
V
OL
ID
OH(SO)
ID
OL(SO)
ID
OH(SI)
ID
OL(SI)
∆ID
O
Oscillator Input Sensitivity OSC_IN
High/Low Level Input
Current
High Level Input Voltage
Low Level Input Voltage
High/Low Input Current
High level Output Voltage
Low Level Output Voltage
ID
O
High, Source Current
ID
O
Low, Source Current
ID
O
High, Sink Current
ID
O
Low, Sink Current
ID
O
Charge Pump Sink
and Source Mismatch
V
I
= 1mA
D
O
= V
P
/2
D
O
= V
P
/2
[IID
O(SI)
I – IID
O(SO)
I]/
[1/2*{IID
O(SI)
]I+IID
O(SO)
I}]*100%
ID
O
VS
T
Charge Pump Current
Variation vs Temperature
High Impedance Leak-
age Current
5
%
-40
o
C<T<85
o
C V
DO
= V
P
/2
(Note 1)
Loop locked, between reference
spikes
I
OFF
±2.5
nA
Note:
ID
O
VS T; Charge pump current variation vs temperature.
[IID
O(SI)@T
I - IID
O(SI)@25o C
I]/IID
O(SI)@25oC
I * 100% and
[IID
O(SO)@T
I - IID
O(SO)@25oC
I]/IID
O(SO)@25oC
I *100%
Dual Serial Input PLL with 2.0 and 1.1 GHz Prescalers
IC WORKS DOCUMENT CONTROL : FDS-011 : REV 1
Revision 1.2
Page 5 of 10
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