256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Features
DDR SDRAM UDIMM
MT9VDDT3272A – 256MB
MT9VDDT6472A – 512MB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• 184-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 256MB (32 Meg x 72) and 512MB (64 Meg x 72)
• Supports ECC error detection and correction
• Vdd = Vddq = +2.5V (-40B: Vdd = Vddq)
• Vddspd = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
architecture; 2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Single rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Gold edge contacts
Figure 1:
184-Pin UDIMM (MO-206)
PCB height: 31.75mm (1.25in)
Options
• Operating temperature
1
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
184-pin DIMM (standard)
–
184-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency
–
5.0ns (200 MHz), 400 MT/s, CL = 3
–
6.0ns (167 MHz), 333 MT/s, CL = 2.5
–
7.5ns (133 MHz), 266 MT/s, CL = 2
2
–
7.5ns (133 MHz), 266 MT/s, CL = 2
2
–
7.5ns (133 MHz), 266 MT/s, CL = 2.5
2
Marking
None
I
G
Y
-40B
-335
-262
-26A
-265
1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1:
Speed
Grade
-40B
-335
-262
-26A
-265
Key Timing Parameters
Industry
Nomenclature
PC3200
PC2700
PC2100
PC2100
PC2100
Notes:
Data Rate (MT/s)
CL = 3
400
–
–
–
–
CL = 2.5
333
333
266
266
266
CL = 2
266
266
266
266
200
t
RCD
t
RP
t
RC
(ns)
15
18
15
20
20
(ns)
15
18
15
20
20
(ns)
55
60
60
65
65
Notes
1
1. The values of
t
RCD and
t
RP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.
PDF: 09005aef808f912d/Source: 09005aef808f8ccd
DD9C32_64x72A.fm - Rev. F 10/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Addressing
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
1 (S0#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 256MB
Base device: MT46V32M8,
1
256Mb DDR SDRAM
Module
Density
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
Module
Bandwidth
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
Memory Clock/
Data Rate
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
3-3-3
3-3-3
2.5-3-3
2.5-3-3
2-2-2
2-3-3
2.5-3-3
2.5-3-3
Part Number
2
Configuration
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
MT9VDDT3272AG-40B__
MT9VDDT3272AY-40B__
MT9VDDT3272AG-335__
MT9VDDT3272AY-335__
MT9VDDT3272AG-262__
MT9VDDT3272AG-26A__
MT9VDDT3272AG-265__
MT9VDDT3272AY-265__
Table 4:
Part Numbers and Timing Parameters – 512MB
Base device: MT46V64M8,
1
512Mb DDR SDRAM
Module
Density
512MB
512MB
512MB
512MB
512MB
512MB
512MB
Module
Bandwidth
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
Memory Clock/
Data Rate
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
3-3-3
3-3-3
2.5-3-3
2.5-3-3
2-2-2
2.5-3-3
2.5-3-3
Part Number
2
MT9VDDT6472AG-40B__
MT9VDDT6472AY-40B__
MT9VDDT6472AG-335__
MT9VDDT6472AY-335__
MT9VDDT6472AG-262__
MT9VDDT6472AG-265__
MT9VDDT6472AY-265__
Notes:
Configuration
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT9VDDT6472AY-40BF1.
PDF: 09005aef808f912d/Source: 09005aef808f8ccd
DD9C32_64x72A.fm - Rev. F 10/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
184-Pin DDR UDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Vref
DQ0
Vss
DQ1
DQS0
DQ2
Vdd
DQ3
NC
NC
Vss
DQ8
DQ9
DQS1
Vddq
CK1
CK1#
Vss
DQ10
DQ11
CKE0
Vddq
DQ16
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
Vss
A9
DQ18
A7
Vddq
DQ19
A5
DQ24
Vss
DQ25
DQS3
A4
Vdd
DQ26
DQ27
A2
Vss
A1
CB0
CB1
Vdd
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
Vss
CB3
BA1
DQ32
Vddq
DQ33
DQS4
DQ34
Vss
BA0
DQ35
DQ40
Vddq
WE#
DQ41
CAS#
Vss
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Vdd
NC
DQ48
DQ49
Vss
CK2#
CK2
Vddq
DQS6
DQ50
DQ51
Vss
NC
DQ56
DQ57
Vdd
DQS7
DQ58
DQ59
Vss
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
184-Pin DDR UDIMM Back
Symbol Pin Symbol Pin Symbol Pin Symbol
Vss
DQ4
DQ5
Vddq
DM0
DQ6
DQ7
Vss
NC
NC
NC
Vddq
DQ12
DQ13
DM1
Vdd
DQ14
DQ15
NC
Vddq
NC
DQ20
A12
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Vss
DQ21
A11
DM2
Vdd
DQ22
A8
DQ23
Vss
A6
DQ28
DQ29
Vddq
DM3
A3
DQ30
Vss
DQ31
CB4
CB5
Vddq
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
Vss
DM8
A10
CB6
Vddq
CB7
Vss
DQ36
DQ37
Vdd
DM4
DQ38
DQ39
Vss
DQ44
RAS#
DQ45
Vddq
S0#
NC
DM5
Vss
DQ46
162 DQ47
163
NC
164 Vddq
165 DQ52
166 DQ53
167
NC
168
Vdd
169
DM6
170 DQ54
171 DQ55
172 Vddq
173
NC
174 DQ60
175 DQ61
176
Vss
177
DM7
178 DQ62
179 DQ63
180 Vddq
181
SA0
182
SA1
183
SA2
184 Vddspd
PDF: 09005aef808f912d/Source: 09005aef808f8ccd
DD9C32_64x72A.fm - Rev. F 10/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A0–A12
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0 and BA1) or all device banks (A10 HIGH). The address inputs also provide the
op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE REGISTER
command.
Bank address:
BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied.
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output
data (DQ and DQS) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and CKE disables (registered LOW) the internal
clock, input buffers, and output drivers.
Input data mask:
DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH, along with that input data, during a write access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of
DQ and DQS pins.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Chip selects:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Presence-detect address inputs:
These pins are used to configure the SPD EEPROM address
range on the I
2
C bus.
Serial clock for SPD EEPROM:
SCL is used to synchronize the presence-detect data transfer
to and from the module.
Check bits.
Data input/output:
Data bus.
Data strobe:
Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data. Used to capture data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the presence-detect portion of the module.
Power supply:
+2.5V ±0.2V (-40B: +2.6V ±0.1V)
SPD EEPROM power supply:
+2.3V to +3.6V.
SSTL_2 reference voltage (Vdd/2).
Ground.
No connect:
These pins are not connected on the module.
BA0, BA1
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
CKE0
DM0–DM8
Input
Input
Input
Input
RAS#, CAS#,
WE#
S0#
SA0–SA2
SCL
CB0–CB7
DQ0–DQ63
DQS0–DQS8
SDA
Vdd/Vddq
Vddspd
Vref
Vss
NC
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Supply
Supply
Supply
Supply
–
PDF: 09005aef808f912d/Source: 09005aef808f8ccd
DD9C32_64x72A.fm - Rev. F 10/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
S0#
DQS0
DM9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS# DQS
DQ
DQ
DQ
U5
DQ
DQ
DQ
DQ
DQ
CK0
CK0#
U4–U6
DQS4
DM13
DM CS# DQS
DQ
DQ
DQ
U1
DQ
DQ
DQ
DQ
DQ
DQS5
DM14
DM CS# DQS
DQ
DQ
DQ
U2
DQ
DQ
DQ
DQ
DQ
DQS6
DM15
DM CS# DQS
DQ
DQ
DQ
U3
DQ
DQ
DQ
DQ
DQ
DQS7
DM16
DM CS# DQS
DQ
DQ
DQ
DQ
U4
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
DQ
DQ
U9
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ
DQ
DQ
U8
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ
DQ
DQ
U7
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
DQ
DQ
DQ
U6
DQ
DQ
DQ
DQ
DQ
SCL
U10
SPD EEPROM
WP A0
A1
A2
SDA
CK1
CK1#
CK2
CK2#
U1–U3
V
SS
SA0 SA1 SA2
U7–U9
BA0, BA1
A0–A12
RAS#
CAS#
WE#
CKE0
BA0, BA1: DDR SDRAM
A0–A12: DDR SDRAM
RAS#: DDR SDRAM
CAS#: DDR SDRAM
WE#: DDR SDRAM
CKE0: DDR SDRAM
Vddspd
Vdd/Vddq
Vref
Vss
SPD EEPROM
DDR SDRAM
DDR SDRAM
DDR SDRAM
PDF: 09005aef808f912d/Source: 09005aef808f8ccd
DD9C32_64x72A.fm - Rev. F 10/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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