DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD72001-11, 72001-A8
MULTI-PROTOCOL SERIAL CONTROLLERS
DESCRIPTION
The
µ
PD72001-11 is an MPSC (Multi-Protocol Serial Controller) which is a general-purpose communication LSI
equipped with two sets of bidirectional parallel/serial converter circuits for data communication. This controller has
a transmitter function to convert the parallel data output by a data terminal into serial data and transmit this data to
a data transmission system such as a modem, and a receiver function to convert the serial data output by the data
transmission system into parallel data.
The MPSC can be used with data communications equipment with a variety of communication modes such as the
generally and widely used start-stop synchronization mode, and the HDLC mode which is used for high-speed
communication.
The
µ
PD72001-A8 is a low-voltage model.
For this product, the following documents are separately available. Read these documents as well as this Data
Sheet.
• User’s Manual (S12472E)
• Application Notes
FEATURES
• Two sets of parallel/serial circuits supporting three modes: start-stop synchronization, character synchronization,
and bit synchronization modes
→
Easy application to a system supporting two or more communication protocols such as a protocol converter or
ISDN terminal adapter
• DPLL (Digital Phase Locked Loop), baud rate generator, and crystal oscillation circuit for transmission/reception
clock
→
Helps reduce cost by decreasing the number of external circuits
• Many variations with power-saving features and small package size
→
Easy application to portable terminals and high-accuracy portable terminals
The features common to the
µ
PD72001-11 and 72001-A8 are explained as the features of the MPSC in this
document.
Document No. S12184EJ7V0DS00 (7th edition)
Date Published November 1997 N
Printed in Japan
½
(I) (S12753E)
(II) (On preparation)
(III) (On preparation)
The information in this document is subject to change without notice.
The mark
shows major revised points.
©
1997
µ
PD72001-11, 72001-A8
ORDERING INFORMATION
Part Number
Package
40-pin plastic DIP (600 mil)
44-pin plastic QFP (10
×
10 mm) (resin thickness: 1.45 mm)
52-pin plastic QFP (14
×
14 mm) (resin thickness: 2.7 mm)
52-pin plastic QFJ (750
×
750 mil)
40-pin plastic DIP (600 mil)
44-pin plastic QFP (10
×
10 mm) (resin thickness: 1.45 mm)
52-pin plastic QFP (14
×
14 mm) (resin thickness: 2.7 mm)
µ
PD72001C-11
µ
PD72001G-11-22
µ
PD72001GC-11-3B6
µ
PD72001L-11
µ
PD72001C-A8
µ
PD72001G-A8-22
µ
PD72001GC-A8-3B6
2
µ
PD72001-11, 72001-A8
SPECIFICATIONS
Item
Part number
Supply voltage
System clock frequency
Maximum transfer rate
Process
Internal circuit
5 V
±10
%
11 MHz MAX.
2.2 Mbps
CMOS
Parallel/serial converter circuit: Full-duplex channel
×
2
Transmit buffer : Double
Receive buffer : Quadruple
Interrupt control function
DMA request signal output: 2 for transmission, 2 for reception
Overrun error detection
DPLL
Baud rate generator
Crystal oscillation circuit for transmission/reception clock generation
Self-loopback test function
Standby function
General-purpose I/O pin: 4 pins
×
2
Start-stop
synchronization
Character bit length: 5, 6, 7, 8
Stop bit length: 1, 1.5, 2
Clock rate:
×1, ×16, ×32, ×64
Parity generation, check
Framing error detection
Break generation, detection
Operation mode: Mono-sync, Bi-sync, External sync
Character bit length: 5, 6, 7, 8
SYNC character bit length: 6, 8
Character synchronization: Internal/external
BCS (Block Check Sequence) generation, check:
CRC-16
CRC-CCITT
Parity generation, check
SYNC character automatic transmission, detection, rejection
Operation mode:
HDLC (High-level Data Link Control)
SDLC (Synchronous Data Link Control)
SDLC Loop
Flag transmission, detection
Zero insertion, rejection
Address field detection (1 byte)
FCS (Frame Check Sequence) generation, detection
Short frame detection
Abort automatic transmission, detection
Idle detection
Go Ahead detection
Transmit number data control
Specifications
µ
PD72001-11
3.3 V
±0.3
V
µ
PD72001-A8
8 MHz MAX. (at T
A
= –10 to +70
°C)
7.14 MHz MAX. (at T
A
= –40 to +85
°C)
1.6 Mbps (at T
A
= –10 to +70
°C)
1.43 Mbps (at T
A
= –40 to +85
°C)
Communication protocol
COP
(Character
Oriented
Protocol)
BOP
(Bit Oriented
Protocol)
Processing data format
Encode/decode of NRZ (Non-Return to Zero)
Encode/decode of NRZI (Non-Return to Zero Inverted)
Encode/decode of FM (Frequency Modulation)
Decode in Manchester mode
3
µ
PD72001-11, 72001-A8
PIN CONFIGURATION (Top View)
• 40-pin plastic DIP (600 mil) :
µ
PD72001C-11,
µ
PD72001C-A8
DCDA
D7
D6
D5
D4
D3
D2
D1
D0
GND
WR
RD
C/D
B/A
PRO
PRI
INTAK
INT
CTSB
DCDB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CTSA
R
X
DA
XI1A/STR
X
CA
XI2A/SYNCA
TR
X
CA
T
X
DA
RTSA
DRQR
X
A
RESET
CLK
V
DD
DRQT
X
A
DTRA/DRQT
X
B
DTRB/DRQR
X
B
RTSB
T
X
DB
XI2B/SYNCB
XI1B/STR
X
CB
R
X
DB
TR
X
CB
• 44-pin plastic QFP (10
×
10 mm) :
µ
PD72001G-11-22,
µ
PD72001G-A8-22
RTSB
DTRB/DRQR
X
B
DTRA/DRQT
X
B
DRQT
X
A
V
DD
V
DD
CLK
RESET
DRQR
X
A
RTSA
T
X
DA
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
T
X
DB
XI2B/SYNCB
XI1B/STR
X
CB
R
X
DB
TR
X
CB
IC
DCDB
CTSB
INT
INTAK
PRI
PRO
B/A
C/D
RD
WR
GND
GND
D0
D1
D2
D3
IC: Internally Connected (Leave this pin unconnected)
4
TR
X
CA
XI2A/SYNCA
XI1A/STR
X
CA
R
X
DA
CTSA
IC
DCDA
D7
D6
D5
D4
µ
PD72001-11, 72001-A8
• 52-pin plastic QFP (14
×
14 mm) :
µ
PD72001GC-11-3B6,
µ
PD72001GC-A8-3B6
NC
NC
RTSA
DRQR
X
A
RESET
CLK
V
DD
V
DD
DRQT
X
A
DTRA/DRQT
X
B
DTRB/DRQR
X
B
NC
NC
T
X
DA
TR
X
CA
XI2A/SYNCA
XI1A/STR
X
CA
R
X
CA
CTSA
IC
DCDA
D7
D6
D5
D4
D3
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
RTSB
T
X
DB
XI2B/SYNCB
XI1B/STR
X
CB
R
X
DB
TR
X
CB
IC
DCDB
CTSB
INT
INTAK
PRI
PRO
NC : No Connection
IC : Internally Connected (Leave this pin unconnected.)
• 52-pin plastic QFJ (750
×
750 mil) :
µ
PD72001L-11
D3
D4
D5
D6
D7
DCDA
NC
CTSA
R
X
DA
XI1A/STR
X
CA
XI2A/SYNCA
TR
X
CA
T
X
DA
D2
NC
D1
NC
D0
GND
GND
WR
RD
C/D
NC
B/A
NC
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
NC
D2
NC
D1
D0
GND
GND
WR
RD
C/D
B/A
NC
NC
NC
RTSA
DRQR
X
A
NC
RESET
CLK
V
DD
V
DD
DRQT
X
A
DTRA/DRQT
X
B
NC
DTRB/DRQR
X
B
NC
PRO
PRI
INTAK
INT
CTSB
DCDB
NC
TR
X
CB
R
X
DB
XI1B/STR
X
CB
XI2B/SYNCB
T
X
DB
RTSB
5
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