DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD72107
LAP-B CONTROLLER
Link Access Procedure Balanced mode
The
µ
PD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single
chip.
FEATURES
• Complied with ITU-T recommended X.25 (LAP-B84
edition)
HDLC frame control
Sequence control
Flow control
• ITU-T recommended X.75 supported
• TTC standard JT-T90 supported
• Optional functions
Option frame
Global address frame
Error check deletion frame
• Powerful test functions
Data loopback function
Loopback test link function
Frame trace function
• Abundant statistical information
• Detailed mode setting function
• Modem control function
• On-chip DMAC (Direct Memory Access Controller)
24-bit address
Byte/word transfer enabled (switch with external pin)
• Memory-based interface
Memory-based command
Memory-based status
Memory-based transmit/receive data
• MAX.4 Mbps serial transfer rate
• NRZ, NRZI coding
ORDERING INFORMATION
Part Number
Package
64-pin plastic shrink DIP (750 mils)
80-pin plastic QFP (14 x 14 mm)
68-pin plastic QFJ (950 x 950 mils)
µ
PD72107CW
µ
PD72107GC-3B9
µ
PD72107L
The information in this document is subject to change without notice.
Document No. S12962EJ5V0DS00 (5th edition)
Date Published October 1998 N CP(K)
Printed in Japan
©
1998
µ
PD72107
BLOCK DIAGRAM
D0-D7
A16D8
-A23D15
A0-A15
IORD
IOWR
MRD
MWR
UBE
CS
ASTB
AEN
READY
HLDRQ
HLDAK
CRQ
INT
CLRINT
B/W
PU
V
CC
GND
RESET
CLK
TxC
TxD
Internal controller
TxFIFO
Transmitter
RTS
CTS
Bus
interface
Internal bus
CD
Receiver
RxFIFO
DMAC
RxC
RxD
Name
Bus interface
Internal controller
DMAC
(Direct Memory
Access Controller)
TxFIFO
RxFIFO
Transmitter
Receiver
Internal bus
Function
An interface between the
µ
PD72107 and external memory or external host processor
Manages LAP-B protocol including control of the DMAC block, transmitter block, and receiver block
Controls the transfer of data on the external memory to the internal controller or transmitter block,
and controls the writing of data in the internal controller or receiver block to the external memory
A 16-byte buffer for when transmit data is sent from the DMAC to the transmitter block
A 32-byte buffer for when receive data is sent from the receiver block to the DMAC
Converts the contents of TxFIFO into an HDLC frame and transmits it as serial data
Receives HDLC frame and writes internal data to RxFIFO
An 8-bit address bus and 8-bit data bus that connect the internal controller, DMAC, FIFO, serial block,
and bus interface block
2
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