DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD72850A
IEEE1394 400Mbps PHY
The
µ
PD72850A is the 3-port physical layer LSI which complies with the P1394a draft 2.0 specifications.
The
µ
PD72850A works up to 400 Mbps. It is an upgrade of NEC's
µ
PD72850.
FEATURES
• The Three-port Physical Layer LSI complies to IEEE P1394a draft 2.0
• Connection debounce
• Arbitration enhancements
• Arbitrated short bus reset
• Ack-accelerated arbitration
• Fly-by concatenation
• Multiple-speed packet concatenation
• Arbitration enhancements and cycle start (controlled by the Link layer)
• Performance optimization via PHY pinging
• Priority arbitration (controlled by the Link layer)
• Data rate: 393.216 / 196.608 / 98.304 Mbps
• Compliant with Suspend/Resume function as defined in P1394a draft 2.1
• 3.3 V single power supply
• Electrical isolated Link interface
• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency
• System power management by signaling of node power class information
• Cable power monitor (CPS) is equipped
• Fully interoperable with IEEE1394 std 1394 Link (FireWire
TM
, i.LINK
TM
)
• Cable bias and terminal voltage driver supply function (for 3-port each)
• Separate digital power and analog GND
• Enable/Disable port control switch when power supply is powered on
• Support Suspend/Resume Off mode (Compliant with P1394a draft 1.3)
• Number of supported port are selectable
• 1port, 2port, 3port. This selection is only under Suspend/Resume Off mode
• Compliant with MD8405E (FUJIFILM MICRODEVICES CO., LTD)
ORDERING INFORMATION
Part number
Package
80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
µ
PD72850AGK-9EU
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14452EJ1V0DS00 (1st edition)
Date Published October 1999 NS CP(K)
Printed in Japan
1999
µ
PD72850A
BLOCK DIAGRAM
CMC
PC0
PC1
PC2
PORTDIS
PSEL
SUS/RES
LREQ
LPS
DIRECT
SCLK
LKON
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
TpA0p
TpA0n
Cable
Port1
TpB0p
TpB0n
Arbitration
and Control
State Machine
Logic
Cable
Port2
Link
Interface
I/O
Cable
Port3
TpA1p
TpA1n
TpB1p
TpB1n
TpA2p
TpA2n
TpB2p
TpB2n
TpBias0
TpBias1
TpBias2
R0
R1
XI
XO
FIL0
FIL1
Receive Data
Decoder and
Retimer
Voltage
and
Current
Generator
Crystal
Oscillator
PLL
System
and
Transmit
Clock
Generator
RESETB
CPS
Cable
Power
Status
Transmit Data
Encoder
2
Data Sheet S14452EJ1V0DS00
µ
PD72850A
PIN CONFIGURATION (Top View)
• 80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
PC1
PC0
CMC
DGND
LPS
LREQ
DV
DD
DGND
SCLK
DV
DD
DGND
CTL0
CTL1
DV
DD
D0
D1
DGND
D2
D3
DGND
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
DV
DD
PC2
LKON
DIRECT
IC(H)
IC(H)
DGND
AV
DD
AGND
SUS/RES
AGND
AGND
AGND
AV
DD
PSEL
AGND
PORTDIS
AV
DD
AGND
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
TpA0p
TpA0n
TpB0p
TpB0n
TpA1p
TpA1n
TpB1p
TpB1n
TpA2p
TpA2n
TpB2p
TpB2n
TpBias0
TpBias1
TpBias2
AV
DD
AGND
CPS
RI1
RI0
D4
D5
DGND
D6
D7
DV
DD
DV
DD
DV
DD
DGND
RESETB
AV
DD
AGND
AGND
FIL1
FIL0
AV
DD
XI
XO
AGND
AV
DD
Data Sheet S14452EJ1V0DS00
3
µ
PD72850A
PIN NAME
AGND
AV
DD
CMC
CPS
CTL0
CTL1
D0-D7
DGND
Direct
DV
DD
FIL0
FIL1
IC(H)
LKON
LPS
LREQ
PC0-PC2
PORTDIS
PSEL
RESETB
RI0
RI1
SCLK
SUS/RES
TpA0n
TpA0p
TpA1n
TpA1p
TpA2n
TpA2p
TpB0n
TpB0p
TpB1n
TpB1p
TpB2n
TpB2p
TpBias0
TpBias1
TpBias2
XI
XO
: Analog GND
: Analog Power
: Configuration Manager Capable
: Cable Power Status
: Link Interface Control (bit 0)
: Link Interface Control (bit 1)
: Data Input/Output
: Digital GND
: PHY/Link Isolation Barrier Control Input
: Digital V
DD
: APLL Filter Ground
: APLL Filter
: Internally Connected (High Clamped)
: Link-on Signal Output
: Link Power Status Input
: Link Request Input
: Power Class Set Input
: Port Disable
: Support Number of Port Select
: Power on Reset Input
: Reference Power Set, Connect Resistor 0
: Reference Power Set, Connect Resistor 1
: Link Control Output Clock
: Suspend/Resume Function Select
: First Port Twisted Pair Cable A Negative Phase I/O
: First Port Twisted Pair Cable A Positive Phase I/O
: Second Port Twisted Pair Cable A Negative Phase I/O
: Second Port Twisted Pair Cable A Positive Phase I/O
: Third Port Twisted Pair Cable A Negative Phase I/O
: Third Port Twisted Pair Cable A Positive Phase I/O
: First Port Twisted Pair Cable B Negative Phase I/O
: First Port Twisted Pair Cable B Positive Phase I/O
: Second Port Twisted Pair Cable B Negative Phase I/O
: Second Port Twisted Pair Cable B Positive Phase I/O
: Third Port Twisted Pair Cable B Negative Phase I/O
: Third Port Twisted Pair Cable B Positive Phase I/O
: First port Twisted Pair Output
: Second Port Twisted Pair Output
: Third Port Twisted Pair Output
: Crystal Oscillator Connection XI
: Crystal Oscillator Connection XO
4
Data Sheet S14452EJ1V0DS00
µ
PD72850A
CONTENTS
1. PIN
1.1
1.2
1.3
1.4
1.5
1.6
FUNCTIONS ..................................................................................................................................... 7
Cable Interface Pins......................................................................................................................... 7
Link Interface Pins ........................................................................................................................... 8
Control Pins...................................................................................................................................... 8
IC........................................................................................................................................................ 9
Power Supply Pins........................................................................................................................... 9
Other Pins......................................................................................................................................... 9
2. PHY REGISTERS ................................................................................................................................... 10
2.1 Complete Structure for PHY Registers ........................................................................................ 10
2.2 Port Status Page (Page 000) ......................................................................................................... 13
2.3 Vendor ID Page (Page 001) ........................................................................................................... 14
3. INTERNAL FUNCTION .......................................................................................................................... 15
3.1 Link Interface.................................................................................................................................. 15
3.1.1 Connection Method............................................................................................................................... 15
3.1.2 LPS (Link Power Status)....................................................................................................................... 15
3.1.3 LREQ, CTL0,CTL1, and D0-D7 Pins .................................................................................................... 15
3.1.4 SCLK..................................................................................................................................................... 15
3.1.5 LKON .................................................................................................................................................... 16
3.1.6 Direct .................................................................................................................................................... 16
3.1.7 Isolation Barrier..................................................................................................................................... 16
3.2 Cable Interface ............................................................................................................................... 18
3.2.1 Connections .......................................................................................................................................... 18
3.2.2 Cable Interface Circuit .......................................................................................................................... 19
3.2.3 Unused Ports ........................................................................................................................................ 19
3.2.4 CPS....................................................................................................................................................... 19
3.3 Suspend/Resume........................................................................................................................... 19
3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 19
3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 19
3.4 PLL and Crystal Oscillation Circuit.............................................................................................. 20
3.4.1 Crystal Oscillation Circuit...................................................................................................................... 20
3.4.2 PLL ....................................................................................................................................................... 20
3.5 PC0-PC2, CMC................................................................................................................................ 20
3.6 RESETB........................................................................................................................................... 20
3.7 RI1, RI0 ............................................................................................................................................ 20
4. PHY/LINK INTERFACE.......................................................................................................................... 21
4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................. 21
4.2 Link-on Indication .......................................................................................................................... 22
4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ....................................................... 23
4.3.1 CTL0,CTL1 ........................................................................................................................................... 23
4.3.2 LREQ .................................................................................................................................................... 23
4.3.3 PHY/Link Interface Timing .................................................................................................................... 27
4.4 Acceleration Control...................................................................................................................... 28
4.5 Transmit Status.............................................................................................................................. 29
5
Data Sheet S14452EJ1V0DS00