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UPD72852AGB-8EU: 产品描述IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI; 文件大小317KB，共48页; 制造商NEC ( Renesas ); 官网地址https://www2.renesas.cn/zh-cn/

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UPD72852AGB-8EU概述

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD72852A

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

The

PD72852A is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.

FEATURES

• The two-port physical layer LSI complies with IEEE1394a-2000

• Fully interoperable with IEEE1394 std 1394 Link (FireWire

, i.LINK

)

• Meets Intel

Mobile Power Guideline 2000

• Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-speed

concatenation, arbitration acceleration, fly-by concatenation

• Suspend Debounce timer for ESD

• “BIAS Detected” signal output

• Double speed signal filter for BIAS Ringing

• Small package: 64-pin plastic LQFP

• Super low power : 68 mA (Operating mode)

: 115

A (Suspend mode)

• Data rate: 400/200/100 Mbps

• Supports PHY pinging and remote PHY access packets

• 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)

• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency

• 64-bit flexible register incorporated in PHY register

• Electrically isolated Link interface

• Supports LPS/Link-on as part of PHY/Link interface

• External filter capacitors for PLL not required

• Extended Resume signaling for compatibility with legacy DV devices

• System power management by signaling of node power class information

• Cable power monitor (CPS) is equipped

ORDERING INFORMATION

Part number

Package

64-pin plastic LQFP (10

10)

PD72852AGB-8EU

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No.

Date Published

Printed in Japan

S16725EJ2V0DS00 (2nd edition)

March 2004 NS CP (K)

The mark

shows major revised points.

2003

PD72852A

CONTENTS

1. PIN

1.1

1.2

1.3

1.4

1.5

1.6

FUNCTIONS..................................................................................................................................... 7

Cable Interface Pins ........................................................................................................................ 7

Link Interface Pins .......................................................................................................................... 7

Control Pins ..................................................................................................................................... 8

IC ....................................................................................................................................................... 8

Power Supply Pins .......................................................................................................................... 8

Other Pins ........................................................................................................................................ 9

2. PHY REGISTERS .................................................................................................................................. 10

2.1 Complete Structure for PHY Registers ....................................................................................... 10

2.2 Port Status Page (Page 000) ........................................................................................................ 13

2.3 Vendor ID Page (Page 001)........................................................................................................... 14

2.4 Vendor Dependent Page (Page 111 : Port_select 0000)............................................................ 14

2.5 Vendor Dependent Page (Page 111 : Port_select 0001)............................................................ 15

3. INTERNAL FUNCTION.......................................................................................................................... 16

3.1 Link Interface ................................................................................................................................. 16

3.1.1 Connection Method ............................................................................................................................... 16

3.1.2 LPS (Link Power Status) ....................................................................................................................... 16

3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins..................................................................................................... 16

3.1.4 SCLK..................................................................................................................................................... 16

3.1.5 LKON .................................................................................................................................................... 17

3.1.6 DIRECT................................................................................................................................................. 17

3.1.7 Isolation Barrier ..................................................................................................................................... 17

3.2 Cable Interface............................................................................................................................... 19

3.2.1 Connections .......................................................................................................................................... 19

3.2.2 Cable Interface Circuit........................................................................................................................... 20

3.2.3 Unused Ports ........................................................................................................................................ 20

3.2.4 CPS....................................................................................................................................................... 20

3.3 Suspend/Resume .......................................................................................................................... 20

3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 20

3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 20

3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 21

3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 21

3.4.2 PLL........................................................................................................................................................ 21

3.5

3.6

3.7

3.8

CMC ................................................................................................................................................ 21

PC0-PC2 ......................................................................................................................................... 21

RESETB .......................................................................................................................................... 21

RI1 ................................................................................................................................................... 21

4. PHY/LINK INTERFACE ......................................................................................................................... 22

4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................ 22

4.2 Link-on Indication ......................................................................................................................... 23

4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ...................................................... 24

4.3.1 CTL0, CTL1 .......................................................................................................................................... 24

4.3.2 LREQ .................................................................................................................................................... 24

Data Sheet S16725EJ2V0DS

UPD72852AGB-8EU相似产品对比

	UPD72852AGB-8EU	UPD72852A
描述	IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI	IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

UPD72852AGB-8EU

UPD72852AGB-8EU概述

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