DATA SHEET
MOS INTEGRATED CIRCUIT
ELECTRON DEVICE
µ
PD75238
4 BIT SINGLE-CHIP MICROCOMPUTER
The
µ
PD75238 is a single-chip microcomputer which contains a CPU capable of 1-, 4-, and 8-bit data
processing, ROM, RAM, and I/O ports. In addition, it contains a fluorescent display tube (FIP
;
) controller/driver,
A/D converter, clock timer, timer/pulse generator capable of 14-bit PWM output, serial interface, and vectored
interrupt function.
In comparison with the
µ
PD75217, the
µ
PD75238 has larger ROM and RAM capacity and has been enhanced
in such peripheral facilities as the display function of the FIP controller/driver, I/O ports, A/D converter, serial
interface.
The
µ
PD75238 finds best use in such applications as timer/tuner of VCRs from advanced type to common
type, configuration of one-chip system control microcomputer, advanced CD player, advanced microwave
ovens, etc.
With the
µ
PD75238, the
µ
PD75P238, which is a PROM product, and various development tools including
IE-75001-R and assemblers are available. They can be used for evaluation during system development and
small-volume production.
FEATURES
•
Mass-storage built-in ROM and RAM
• Program memory (ROM) : 32K
×
8
• Data memory (RAM)
to FIP)
: 1K
×
4
•
I/O port: 64 lines (excluding pins dedicated
•
Minimum instruction execution time:
0.67
µ
s (at 6.0 MHz)
•
•
•
•
•
8-bit A/D converter: 8 channels
Enhanced timer/counter function: 5 channels
8-bit serial interface: 2 channels
Application-oriented interrupt functions
PROM version device:
µ
PD75P238
•
Instruction execution time specification func-
tion to allow a wide range of operating
voltages
•
Programmable FIP controller/driver contained
• Number of segments : 9 to 24 segments
• Number of digits
: 9 to 16 digits
ORDERING INFORMATION
Part number
Package
94-pin plastic QFP (20
×
20 mm)
Quality grade
Standard
µ
PD75238GJ-×××-5BG
Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No.
(O.D. No.
Date Published
Printed in Japan
IC-2777A
IC-8177A)
February 1993 P
Major changes in this revision are indicated by stars (5) in the margins.
©
NEC Corporation 1992
µ
PD75238
FUNCTIONS
Item
On-chip memory
I/O lines
(Excluding pins dedicated to FIP)
Function
ROM: 32640
×
8 bits, RAM: 1024
×
4 bits
•
64 lines •
•
•
•
•
•
•
•
•
•
Input : 16 lines
I/O
: 24 lines
Output : 24 lines
Instruction cycle
0.67
µ
s/1.33
µ
s/2.67
µ
s/10.7
µ
s (at 6.0 MHz)
0.95
µ
s/1.91
µ
s/3.82
µ
s/15.3
µ
s (at 4.19 MHz)
122
µ
s (at 32.768 kHz)
Number of segments : 9 to 24 segments
Number of digits
: 9 to 16 digits
Dimmer function
: 8 levels
Pull-down resistors provided by mask option
Key scan interrupt generator
•
Basic interval timer
: Usable as watchdog timer
Fluorescent display tube (FIP)
controller/driver
Timer/counter
5 channels
•
•
•
•
•
•
Timer/event counter
Clock timer
: With buzzer output function
Timer/pulse generator : With 14-bit PWM output function
Event counter
SBI or 3-wire mode
3-wire mode
Serial interface
2 channels
Interrupt
•
•
Allows multiple hardware interrupts.
External interrupts : 3
•
•
•
•
•
•
•
•
•
•
•
Detection of both edges
Detection edge programmable (with noise
elimination)
Detection edge programmable
Rising edge detection
Timer/pulse generator
Timer/event counter
Basic interval timer
Serial interface #0
For key scanning
Clock timer
Serial interface #1
•
External test input : 1
•
Internal interrupts : 5
•
System clock oscillator
Internal test inputs: 2
•
•
•
•
•
Main system clock : 6.0 MHz, 4.19 MHz
Subsystem clock : 32.768 kHz, standard
High-voltage port : Pull-down resistor or open-drain output
Ports 4 and 5
: Pull-up resistor
Port 7
: Pull-down resistor
Mask option
Operating temperature
Operating voltage
Package
-40 to +85
°C
2.7 to 6.0 V (Data held in standby mode: 2.0 to 6.0 V)
94-pin plastic QFP (20
×
20 mm)
2
µ
PD75238
PIN CONFIGURATION
AN0
AV
REF
AV
DD
V
DD
V
DD
X2
X1
IC
XT2
XT1
V
SS
S16/P100
S17/P101
S18/P102
S19/P103
S20/P110
S21/P111
S22/P112
S23/P113
S0/P120
S1/P121
S2/P122
S3/P123
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72
71
1
70
2
69
3
68
4
67
66
5
65
6
64
7
63
8
62
9
61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
AN1
AN2
AN3
AN4/P90
AN5/P91
AN6/P92
AN7/P93
AV
SS
RESET
P00/INT4
P01/SCK0
P02/SO0/SB0
P03/SI0/SB1
P10/INT0
P11/INT1
P12/INT2
P13/TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
P30
P31
P32
P33
P40
P41
P42
P43
V
SS
P50
P51
P52
P53
P60
P61
P62
P63
P70
P71
P72
P73
P80/PPO
P81/SCK1
P82/SO1
P83/SI1
V
DD
Caution Be sure to supply power to the AV
DD
, V
DD
, V
SS
, and AV
SS
pins (pins 3, 4, 5, 11, 30, 48, 65, and 87).
Remark
IC: Internally connected pin (to be grounded)
S4/P130
S5/P131
S6/P132
S7/P133
S8/P140
S9/P141
V
DD
V
LOAD
T15/S10/P142
T14/S11/P143
PH0/T13/S12/P150
PH1/T12/S13/P151
PH2/T11/S14/P152
PH3/T10/S15/P153
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
µ
PD75238GJ-×××-5BG
3
4
Port 0
4
4
P10-P13
P20-P23
P30-P33
P40-P43
Note
P50-P53
Note
P60-P63
P70-P73
4
4
Port 9
10
4
FIP
controller/
driver
f
X
/2
N
8
Clock
output
control
Clock
divider
Stand by
control
Sub
Main
Clock
generator
CPU clock
Φ
Port 10-15 24
S16/P100-S23/P113
V
LOAD
P100-P153
2
10
P80-P83
P90-P93
T0-T9
T10/S15/PH3/P153-
T13/S12/PH0/P150
T14/S11/P143 and
T15/S10/P142
S0/P120-S9/P141
4
4
4
4
4
4
P00-P03
Port 1
CY
SP (8)
SBS (2)
Port 3
Port 4
Port 5
Port 6
Port 7
ROM
program
memory
32640
×
8
Port 8
Decode
and control
RAM data
memory
1024
×
4
Bank
ALU
Program
counter (15)
Port 2
Basic
interval
timer
TI0
INTBT
TI0/P13
PTO0/P20
Timer/event
counter
#0
BLOCK DIAGRAM
INTT0
BUZ/P23
Watch
timer
INTW
General register
PPO/P80
Timer/pulse
generator
INTTPG
SI0/SB1/P03
SO0/SB0/P02
SCK0/P01
Serial
interface 0
INTCSI0
SI1/P83
SO1/P82
SCK1/P81
Serial
interface 1
INT0/P10
INT1/P11
INT2/P12
INT4/P00
Interrupt
control
TI0
PCL/P22
XT1XT2 X1 X2
RESET
V
DD
V
SS
V
DD
Event
counter
8
AN0-AN3
AN4/P90-AN7/P93
AV
DD
AV
REF
AV
SS
A/D
converter
Note
Port 4 and port 5 are N-ch open-drain I/O ports with a
medium withstand voltage of 10 V.
µ
PD75238
Bit sequential
buffer (16)
µ
PD75238
CONTENTS
1.
PIN FUNCTIONS ........................................................................................................................
1.1
1.2
1.3
1.4
PORT PINS ......................................................................................................................................
NON-PORT PINS ............................................................................................................................
PIN INPUT/OUTPUT CIRCUITS ....................................................................................................
CONNECTION OF UNUSED
µ
PD75238 PINS ..............................................................................
7
7
9
11
15
2.
ARCHITECTURE AND MEMORY MAP OF THE
µ
PD75238 ...................................................
2.1
2.2
2.3
DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ................................
GENERAL REGISTER BANK CONFIGURATION ..........................................................................
MEMORY-MAPPED I/O .................................................................................................................
16
16
19
22
3.
INTERNAL CPU FUNCTIONS ....................................................................................................
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
PROGRAM COUNTER (PC) ...........................................................................................................
PROGRAM MEMORY (ROM) ........................................................................................................
DATA MEMORY (RAM) .................................................................................................................
GENERAL REGISTERS ...................................................................................................................
ACCUMULATORS ..........................................................................................................................
STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) .....................................
PROGRAM STATUS WORD (PSW) ..............................................................................................
BANK SELECT REGISTER (BS) .....................................................................................................
27
27
27
29
31
32
32
35
39
4.
PERIPHERAL HARDWARE FUNCTIONS ..................................................................................
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
DIGITAL I/O PORTS .......................................................................................................................
CLOCK GENERATOR ......................................................................................................................
CLOCK OUTPUT CIRCUIT .............................................................................................................
BASIC INTERVAL TIMER ...............................................................................................................
TIMER/EVENT COUNTER .............................................................................................................
CLOCK TIMER .................................................................................................................................
TIMER/PULSE GENERATOR .........................................................................................................
EVENT COUNTER ..........................................................................................................................
SERIAL INTERFACE .......................................................................................................................
A/D CONVERTER ...........................................................................................................................
BIT SEQUENTIAL BUFFER ............................................................................................................
FIP CONTROLLER/DRIVER ............................................................................................................
40
40
49
58
61
63
69
71
77
79
113
119
119
5.
INTERRUPT FUNCTION ............................................................................................................ 131
5.1
5.2
5.3
5.4
5.5
CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT ....................................................
HARDWARE OF THE INTERRUPT CONTROL CIRCUIT ..............................................................
MULTIPLE INTERRUPT PROCESSING CONTROL ......................................................................
VECTOR ADDRESS SHARE INTERRUPT PROCESSING ............................................................
131
133
139
141
INTERRUPT SEQUENCE ................................................................................................................ 138
5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
