DATA SHEET
MOS INTEGRATED CIRCUIT
ELECTRON DEVICE
µ
PD75518(A)
4 BIT SINGLE-CHIP MICROCOMPUTER
The
µ
PD75518(A) is a 75X series four-bit single-chip microcomputer which enables data processing
equivalent to that performed by an eight-bit microcomputer. It is a high-performance product, whose
minimum instruction execution time is 0.67
µ
s, shorter than 0.95
µ
s for the conventional
µ
PD75516. The ROM
and RAM capacities are also larger, and the throughput of the 75X series is further increased. The
µ
PD75517(A)
is suited to controllers of electric parts of automobiles.
FEATURES
•
•
•
•
Higher reliable than the
µ
PD75518
Capacities of program memory, ROM: 32640
×
8 bits
Capacity of data memory, RAM: 1024
×
4 bits
Function for specifying the instruction execution time (useful for high-speed operation and saving power)
• 0.67
µ
s/1.33
µ
s/2.67
µ
s/10.7
µ
s (when the main system clock operates at 6.0 MHz)
• 0.95
µ
s/1.91
µ
s/3.82
µ
s/15.3
µ
s (when the main system clock operates at 4.19 MHz)
• 122
µ
s (when the subsystem clock operates at 32.768 kHz)
•
Built-in A/D converter operable on low voltage
• 8-bit resolution
×
8 channels (Successive approximation system)
• V
DD
= 2.7 to 6.0 V
•
Many I/O lines: 64
•
Enhanced timer function: 4 channels
•
Built-in 8-bit serial interface: Two channels
• Built-in NEC serial bus interface (SBI)
•
Clock operable with ultra-low power consumption (when 5-
µ
A TYP. operates on 3 V.)
•
Product with a built-in PROM available:
µ
PD75P518
APPLICATIONS
Controller of electric parts of automobiles
ORDERING INFORMATION
Part number
Package
80-pin plastic QFP (14 mm
×
20 mm)
Quality grade
Special
µ
PD75518GF(A)-×××-3B9
Remark
×××:
Code number
Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No.
IC-3191
(O.D. No.
IC-8684)
Date Published December 1992 P
Printed in Japan
NEC CORPORATION 1992
µ
PD75518(A)
FUNCTIONS
Item
Built-in memory
ROM
RAM
General registers
Instruction cycle
32640
×
8 bits
1024
×
4 bits
(4-bit
×
8 or 8-bit
×
4)
×
4 banks
• 0.67
µ
s/1.33
µ
s/2.67
µ
s/10.7
µ
s (At 6.0 MHz)
• 0.95
µ
s/1.91
µ
s/3.82
µ
s/15.3
µ
s (At 4.19 MHz)
• 122
µ
s (At 32.768 kHz)
64
16 (Shared with INT, SIO, PPO, and analog input. Seven lines can be pulled
up by software.)
28 (Four lines for LED driving)
• 16 lines can be pulled up by software.
• Four lines can be pulled down by the mask option.
20 (Eight lines for LED driving. Withstand voltage is 10 V. 20 lines can be
pulled up by the mask option.)
8-bit resolution
×
8 channels (Successive approximation system)
• Capable of low-voltage operation: V
DD
= 2.7 to 6.0 V
Four channels
• Timer/event counter
• Basic interval timer
• Timer/pulse generator (14-bit PWM output enabled)
• Clock timer
Serial interface
Two channels
• NEC standard serial bus interface (SBI)/
three-wire SIO: One channel
• General clock synchronous serial interface
(three-wire SIO): One channel
Functions
I/O ports
Total
Number of CMOS
input lines
Number of CMOS
I/O lines
Number of N-ch
open-drain I/O lines
A/D converter
Timer/counter
Interrupt
• Vectored interrupt : Seven sources (External: 3, internal: 4)
• Test input
: Two sources (External: 1, internal: 1)
• Clock test flag is provided.
• Parallel edge detection flag for key scan input is provided.
Instruction set
• Set/reset/test/Boolean operation for bit data
• 4-bit data transfer, arithmetic/logical, increment/decrement, and comparison
instructions
• 8-bit data transfer, arithmetic/logical, increment/decrement, and comparison
instructions
System clock generator
• Ceramic/crystal oscillator for main system clock : 6.0 MHz, 4.19 MHz
• Crystal oscillator for subsystem clock
: 32.768 kHz
V
DD
= 2.7 to 6.0 V
80-pin plastic QFP (14
×
20 mm)
Operating supply voltage
Package
2
µ
PD75518(A)
PIN CONFIGURATION (TOP VIEW)
AN4/P150
AN5/P151
AN6/P152
AN7/P153
P120
P121
P122
P123
P130
P131
P132
AN0
AV
REF
Note
1
2
3
4
5
6
7
8
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
58
57
P133
AV
SS
AN1
AN2
AN3
P140
P141
P142
P143
RESET
X2
X1
IC
XT2
XT1
V
SS
P00/INT4
P01/SCK0
P02/SO0/SB0
P03/SI0/SB1
P10/INT0
P11/INT1
P12/INT2
P13/ TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
P30
V
DD
V
DD
P113
P112
P111
P110
P103
P102
P101
P100
P93
P92
P91
P90
µ
PD75518GF(A)-×××-3B9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
SI1/P83
SO1/P82
SCK1/P81
PPO/P80
KR7/P73
KR6/P72
KR5/P71
KR4/P70
24
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
KR3/P63
KR2/P62
KR1/P61
KR0/P60
P53
P52
P51
P50
V
SS
P43
P42
P41
P40
P33
P32
IC: Internally connected. Connect the IC pin to V
SS
.
Note
Be sure to supply power to both the V
DD
pins.
P31
3
4
Port 0
4
P00 - P03
P10 - P13
P20 - P23
P30 - P33
P40 - P43
Note
P50 - P53
Note
P60 - P63
4
4
Port 9
Port 10
Port 11
Port 12
Port 13
f
X
/2
N
Port 14
Clock divider
Sub
Main
Clock generator
Stand by
control
CPU clock
Φ
Port 15
4
4
P140 - P143
Note
P150 - P153
4
4
4
4
4
P70 - P73
P80 - P83
P90 - P93
P100 - P103
P110 - P113
P120 - P123
Note
P130 - P133
Note
4
4
4
4
4
4
Port 1
CY
Port 2
Port 3
Port 4
Port 5
Port 6
General register
Port 7
Port 8
Decode and
control
RAM data memory
1024
×
4 bits
SBS(2)
SP(8)
ALU
Bank
Basic
interval
timer
INTBT
TI0/P13
PTO0/P20
Timer/event
counter #0
Program counter (15)
INTT0
INTERNAL BLOCK DIAGRAM
BUZ/P23
Watch timer
INTW
PPO/P80
Timer/pulse
generator
INTTPG
ROM program memory
32640
×
8 bits
SI0/SB1/P03
SO0/SB0/P02
SCK0/P01
Serial
interface 0
INTCSI
SI1/P83
SO1/P82
SCK1/P81
Serial
interface 1
INT0/P10
INT1/P11
INT2/P12
Interrupt
control
INT4/P00
Clock output
control
KR0/P60
- KR7/P73
XT1 XT2 X1 X2
PCL/P22
RESET
V
DD
V
SS
Bit se-
quential
buffer (16)
AN0 - AN3
AN4/P150
- AN7/P153
µ
PD75518(A)
AV
REF
AV
SS
A/D
converter
Note
Port 4, Port 5, Port 12, Port 13, and Port 14 are N-ch open-drain
I/O ports with a medium withstand voltage of 10 V.
µ
PD75518(A)
CONTENTS
1.
PIN FUNCTIONS ........................................................................................................................
1.1
1.2
1.3
1.4
1.5
PORT PINS ......................................................................................................................................
NON-PORT PINS ............................................................................................................................
PIN INPUT/OUTPUT CIRCUITS ....................................................................................................
CONNECTION OF UNUSED PINS ................................................................................................
SELECTION OF A MASK OPTION ................................................................................................
7
7
9
10
13
14
2.
ARCHITECTURE AND MEMORY MAP OF THE
µ
PD75518(A) ..............................................
2.1
2.2
2.3
DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ................................
GENERAL REGISTER BANK CONFIGURATION ..........................................................................
MEMORY-MAPPED I/O .................................................................................................................
15
15
19
22
3.
INTERNAL CPU FUNCTIONS ....................................................................................................
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
PROGRAM COUNTER (PC) ...........................................................................................................
PROGRAM MEMORY (ROM) ........................................................................................................
DATA MEMORY (RAM) .................................................................................................................
GENERAL REGISTERS ...................................................................................................................
ACCUMULATORS ..........................................................................................................................
STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) .....................................
PROGRAM STATUS WORD (PSW) ..............................................................................................
BANK SELECT REGISTER (BS) .....................................................................................................
27
27
27
29
31
32
32
35
38
4.
PERIPHERAL HARDWARE FUNCTIONS ..................................................................................
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
DIGITAL I/O PORTS .......................................................................................................................
CLOCK GENERATOR ......................................................................................................................
CLOCK OUTPUT CIRCUIT .............................................................................................................
BASIC INTERVAL TIMER ...............................................................................................................
CLOCK TIMER .................................................................................................................................
TIMER/EVENT COUNTER .............................................................................................................
TIMER/PULSE GENERATOR .........................................................................................................
SERIAL INTERFACE (CHANNEL 0) ...............................................................................................
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
Serial Interface (Channel 0) Functions ........................................................................
Configuration of Serial Interface (Channel 0) ............................................................
Register Functions .........................................................................................................
Signals .............................................................................................................................
Serial Interface (Channel 0) Operation .......................................................................
Transfer Start in Each Mode ........................................................................................
Manipulation of SCK0 Pin Output ...............................................................................
39
39
51
60
63
67
69
75
83
84
84
86
94
100
110
111
5
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