DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P0076
4-BIT SINGLE-CHIP MICROCONTROLLER
The
µ
PD75P0076 replaces the
µ
PD750068’s internal mask ROM with a one-time PROM and features expanded ROM
capacity.
Because the
µ
PD75P0076 supports programming by users, it is suitable for use in prototype testing for system
development using the
µ
PD750064, 750066, and 750068 products, and for use in small-lot production.
Detailed information about function is provided in the following user’s manual.
Be sure to read it before designing:
µ
PD750068 User’s Manual: U10670E
FEATURES
Compatible with
µ
PD750068
Memory capacity:
• PROM : 16384 x 8 bits
• RAM
: 512 x 4 bits
Can operate with same power supply voltage as the mask ROM version
µ
PD750068
V
DD
= 1.8 to 5.5 V
On-chip A/D converter capable of low-voltage operation (AV
REF
= 1.8 to 5.5 V)
8-bit resolution x 8 channels
Small shrink SOP package
ORDERING INFORMATION
Part Number
Package
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
µ
PD75P0076CU
µ
PD75P0076GT
Caution On-chip pull-up resistors by mask option cannot be provided.
The information in this document is subject to change without notice.
Document No. U10232EJ1V0DS00 (1st edition)
Date Published December 1996 N
Printed in Japan
The mark
shows major revised points.
©
1995
µ
PD75P0076
Functional Outline
Parameter
Instruction execution time
Function
• 0.95, 1.91, 3.81, 15.3
µ
s (@ 4.19 MHz with main system clock)
• 0.67, 1.33, 2.67, 10.7
µ
s (@ 6.0 MHz with main system clock)
• 122
µ
s (@ 32.768 kHz with subsystem clock)
16384 x 8 bits
512 x 4 bits
• 4-bit operation: 8 x 4 banks
• 8-bit operation: 4 x 4 banks
12
Connections of on-chip pull-up resistors can be specified by software: 7
Also used for analog input pins: 4
Connections of on-chip pull-up resistors can be specified by software: 12
Also used for analog input pins: 4
13-V withstand voltage
On-chip memory
PROM
RAM
General-purpose register
Input/
output
port
CMOS input
CMOS input/output
12
N-ch open-drain
input/output pins
Total
Timer
8
32
4
•
•
•
channels
8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter)
8-bit basic interval timer/watchdog timer: 1 channel
Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ··· MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
8-bit resolution x 8 channels (1.8 V
≤
AV
REF
≤
V
DD
)
16 bits
•
Φ,
1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19 MHz with main system clock)
•
Φ,
1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0 MHz with main system clock)
• 2, 4, 32 kHz (@ 4.19 MHz with main system clock or
@ 32.768 kHz with subsystem clock)
• 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock)
A/D converter
Bit sequential buffer
Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupts
Test input
System clock oscillator
External: 3, Internal: 4
External: 1, Internal: 1
• Ceramic or crystal oscillator for main system clock oscillation
• Crystal oscillator for subsystem clock oscillation
STOP/HALT mode
T
A
= –40 to +85 ˚C
V
DD
= 1.8 to 5.5 V
• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
Standby function
Operating ambient temperature
Power supply voltage
Package
2
µ
PD75P0076
CONTENTS
1. PIN CONFIGURATION (Top View) ...................................................................................................
2. BLOCK DIAGRAM ............................................................................................................................
3. PIN FUNCTIONS ...............................................................................................................................
3.1
3.2
3.3
3.4
Port Pins ...................................................................................................................................................
Non-port Pins ...........................................................................................................................................
Equivalent Circuits for Pins ....................................................................................................................
4
5
6
6
7
9
Handling of Unused Pins ......................................................................................................................... 12
4. SWITCHING BETWEEN Mk I AND Mk II MODES ............................................................................ 13
4.1
4.2
Difference betweens Mk I Mode and Mk II Mode .................................................................................... 13
Setting of Stack Bank Selection (SBS) Register .................................................................................... 14
5. DIFFERENCES BETWEEN
µ
PD75P0076 AND
µ
PD750064, 750066 AND 750068 ........................ 15
6. MEMORY CONFIGURATION ............................................................................................................ 16
7. INSTRUCTION SET ........................................................................................................................... 18
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................... 29
8.1
8.2
8.3
8.4
Operation Modes for Program Memory Write/Verify ............................................................................. 29
Steps in Program Memory Write Operation ............................................................................................ 30
Steps in Program Memory Read Operation ............................................................................................ 31
One-time PROM Screening ..................................................................................................................... 32
9. ELECTRICAL SPECIFICATIONS...................................................................................................... 33
10. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................ 49
11. PACKAGE DRAWINGS .................................................................................................................... 51
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 53
APPENDIX A DIFFERENCES AMONG
µ
PD75068, 750068 AND 75P0076 ......................................... 54
APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 55
APPENDIX C RELATED DOCUMENTS ................................................................................................. 58
3
µ
PD75P0076
1. PIN CONFIGURATION (Top View)
• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µ
PD75P0076CU
• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
µ
PD75P0076GT
XT1
XT2
RESET
X1
X2
P33/MD3
P32/MD2
P31/MD1
P30/MD0
AV
SS
P63/KR3/AN7
P62/KR2/AN6
P61/KR1/AN5
P60/KR0/AN4
P113/AN3
P112/AN2
P111/AN1
P110/AN0
AV
REF
V
PP
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
P40/D0
P41/D1
P42/D2
P43/D3
P50/D4
P51/D5
P52/D6
P53/D7
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P10/INT0
P11/INT1
P12/TI1/INT2
P13/TI0
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
In normal operation mode, make sure to connect V
PP
directly to V
DD
.
Pin Identification
AN0 to AN7
AV
REF
AV
SS
BUZ
D0 to D7
INT0, INT1, INT4
INT2
KR0 to KR3
MD0 to MD3
P00 to P03
P10 to P13
P20 to P23
P30 to P33
P40 to P43
P50 to P53
P60 to P63
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Analog Input 0 to 7
Analog Reference
Analog Ground
Buzzer Clock
Data Bus 0 to 7
External Vectored Interrupt 0, 1, 4
External Test Input 2
Key Return
Mode Selection 0 to 3
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
P110 to P113
PCL
PTO0, PTO1
RESET
SB0, SB1
SCK
SI
SO
TI0, TI1
V
DD
V
PP
V
SS
X1, X2
XT1, XT2
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Port 11
Programmable Clock
Programmable Timer Output 0, 1
Reset Input
Serial Data Bus 0, 1
Serial Clock
Serial Input
Serial Output
Timer Input 0, 1
Positive Power Supply
Programmable Power Supply
Ground
Main System Clock Oscillation 1, 2
Subsystem Clock Oscillation 1, 2
4
µ
PD75P0076
2. BLOCK DIAGRAM
BASIC INTERVAL
TIMER/WATCHDOG
TIMER
INTBT
BUZ/P23
WATCH TIMER
INTW
INTW
INTT0
PROGRAM COUNTER
PORT0
4
P00 to P03
SP (8)
ALU
CY
PORT1
4
P10 to P13
PORT2
4
P20 to P23
P30/MD0 to
P33/MD3
P40/D0 to
P43/D3
P50/D4 to
P53/D7
P60 to P63
PORT3
SBS
BANK
PORT4
4
TI0/P13
PTO0/P20
8-BIT
TIMER/
EVENT
CASCADED
COUNTER#0
16-BIT
TIMER/
EVENT
8-BIT
COUNTER
TIMER/
EVENT
COUNTER#1
4
TI1/P12/INT2
PTO1/P21
GENERAL REG.
PORT5
4
INTT1
SI/SB1/P03
SO/SB0/P02
SCK/P01
INTCSI TOUT0
INT0/P10
INT1/P11
INT4/P00
INT2/P12/TI1
KR0/P60 to
4
KR3/P63
AN0/P110 to
AN3/P113
AN4/P60 to
AN7/P63
AV
REF
AV
SS
INTERRUPT
CONTROL
CLOCKED SERIAL
INTERFACE
PROGRAM
MEMORY
(PROM)
16384 x 8 BITS
PORT6
DATA MEMORY
(RAM)
512 x 4BITS
4
PORT11
4
P110 to P113
DECODE
AND
CONTROL
BIT SEQ. BUFFER (16)
fx/2
N
CPU CLOCK
Φ
4
4
SYSTEM CLOCK
CLOCK
CLOCK GENERATOR
STAND BY
OUTPUT
DIVIDER
CONTROL
CONTROL
SUB
MAIN
A/D CONVERTER
PCL/P22
XT1 XT2 X1 X2
V
PP
V
DD
V
SS
RESET
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
