DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P108B
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The
µ
PD75P108B is a version of the
µ
PD75108 in which the on-chip mask ROM is replaced by one-time
PROM which can be written to once only, or EPROM which is capable of program write, erasure and rewrite.
Also, since the
µ
PD75P108B is capable of program write by a user, it can easily be exchanged with the mask
version, allowing evaluation at low voltage.
Detailed functional descriptions are shown in the following User’s Manual. Be sure to read for designations.
µ
PD751×× Series User’s Manual : IEM-922
FEATURES
•
Version with on-chip PROM, allowing low-voltage operation V
DD
= 2.7 to 6.0 V
•
µ
PD75108 compatible
•
Memory capacity
•
Program memory (PROM) : 8064
×
8 bits
•
Data memory (RAM)
: 512
×
4 bits
•
Correspondence to QTOP™ microcomputer
ORDERING INFORMATION
Ordering Code
Package
64-pin plastic shrink DIP (750 mil)
64-pin ceramic shrink DIP (with window)
64-pin plastic QFP (14
×
20 mm, 1.0 mm pitch)
On-Chip ROM
One-time PROM
EPROM
One-time PROM
µ
PD75P108BCW
µ
PD75P108BDW
µ
PD75P108BGF-3BE
Note
5
There is no on-chip pull-up resistor function by means of a mask option.
QUALITY GRADE
Standard
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
In this ducument, common parts of one-time PROM products and EPROM products are represented as
PROM.
The information in this document is subject to change without notice.
The mark
5
shows major revised points.
Document No. IC-2580C
(O. D. No.
IC-7987C)
Date Published December 1993 P
Printed in Japan
© NEC Corporation 1989
µ
PD75P108B
PIN CONFIGURATION (TOP VIEW)
64-pin plastic shrink DIP (750 mil)
64-pin ceramic shrink DIP
(with window)
P13/INT3
P12/INT2
P11/INT1
P10/INT0
PTH03
PTH02
PTH01
PTH00
TI0
TI1
P23
P22/PCL
P21/PTO1
P20/PTO0
P03/SI
P02/SO
P01/SCK
P00/INT4
P123
P122
P121
P120
P133
P132
P131
P130
P143
P142
P141
P140
V
PP
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
SS
P90
P91
P92
P93
P80
P81
P82
P83
P70
P71
P72
P73
P60
P61
P62
P63
X1
X2
RESET
P50
P51
P52
P53
P40
P41
P42
P43
P30/MD0
P31/MD1
P32/MD2
P33/MD3
µ
PD75P108BCW
µ
PD75P108BDW
2
µ
PD75P108B
64-pin plastic QFP (14
×
20 mm, 1.0 mm pitch)
P41
P40
P53
P52
P51
P50
RESET
X2
X1
P63
P62
P61
P60
P73
P72
P71
P70
P83
P82
64 636261605958575655545352
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32
P42
P43
P30/MD0
P31/MD1
P32/MD2
P33/MD3
V
DD
V
PP
P140
P141
P142
P143
P130
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P131
P132
P133
P120
P121
P122
P123
P00/INT4
P01/SCK
P02/SO
P03/SI
P20/PTO0
P21/PTO1
P22/PCL
P23
T11
T10
PTH00
PTH01
µ
PD75P108BGF-3BE
m
P81
P80
P93
P92
P91
P90
V
SS
P13/INT3
P12/INT2
P11/INT1
P10/INT0
PTH03
PTH02
3
µ
PD75P108B
OVERVIEW OF FUNCTIONS
Item
Basic instructions
Minimum instruction
execution time
ROM
Internal memory
RAM
General register
512
×
4
4-bits
×
8
×
4 banks (memory mapping)
3 types of accumulators corresponding to bit length of manipulated data
• 1-bit accumulator (CY),
4-bit accumulator (A),
8-bit accumulator (XA)
Total 58
• CMOS input pins
• CMOS input/output pins (LED direct drive capability)
• Middle-high voltage N-ch open-drain input/output pins
(LED direct drive capability)
• Comparator input pins (4-bit precision)
• 8-bit timer/event counter
×
2
• 8-bit basic interval timer (watchdog timer applicable)
• Two transfer modes
• Serial transmity receive mode
• Serial receive mode
• LSB-first/MSB-first switchable
Vectored interrupt
Test input
Standby
External : 3, internal : 4
External : 2
• STOP/HALT mode
• Various bit manipulation instructions (set, reset, test, boolean operation)
Instruction set
• 8-bit data transfer, comparison, operation, increment/decrement instructions
• 1-byte relative branch instruction
• GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1
byte
Others
• Bit manipulation memory (bit sequential buffer : 16 bits) on-chip
• 64-pin plastic shrink DIP (750 mil)
• 64-pin ceramic shrink DIP (with window)
• 64-pin plastic QFP (14
×
20mm, 1.0 mm pitch)
43
0.95
µ
s, 1.91
µ
s, 15.3
µ
s (4.19 MHz operation)
3-stage switching capability
8064
×
8
Description
Accumulator
Input/output port
: 10
: 32
: 12
: 4
Timer/counter
8-bit serial interface
5
Package
4
BASIC
INTERVAL
TIMER
PROGRAM
COUNTER (13)
PORT
0
4
4
P10-P13
P00-P03
PORT 1
BANK
PORT 2
PORT 3
GENERAL REG.
PORT 4
4
4
PORT 5
PORT 6
PORT 7
4
4
P20-P23
P30-P33
/MD0-MD3
P40-P43
ALU
CY
SP(8)
BIT SEQ.
BUFFER
(16)
BLOCK DIAGRAM
INTBT
TI0
PTO0/P20
TIMER/EVENT
COUNTER
#0
INTT0
TI1
PTO1/P21
TIMER/EVENT
COUNTER
#1
INTT1
SI/P03
DECODE
AND
CONTROL
RAM DATA
MEMORY
512
×
4 BITS
SO/P02
SCK/P01
SERIAL
INTERFACE
ROM
PROGRAM
MEMORY
8064
×
8 BITS
P50-P53
4
4
P60-P63
INTSIO
P70-P73
PORT 8
4
INT0/P10
P80-P83
PORT 9
f
XX
/ 2
CLOCK
DIVIDER
CLOCK
GENERATOR
N
INT1/P11
INT2/P12
INT3/P13
INT4/P00
INTER-
RUPT
CONTROL
4
P90-P93
PTH00-PTH03
4
CLOCK
OUTPUT
CONTROL
STAND BY
CONTROL
CPU CLOCK
Φ
PORT 12
4
P120-P123
PORT 13
4
PROGRAM-
MABLE
THRESHOLD
PORT #0
P130-P133
V
PP
V
DD
V
SS
RESET
PORT 14
4
µ
PD75P108B
PCL/P22
X1
X2
P140-P143
5
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