DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P218
4-BIT SINGLE-CHIP MICROCOMPUTER
The
µ
PD75P218 is a one-time PROM version that can be written to only once or an EPROM version that allows
program writing, erasing, and rewriting, of the
µ
PD75218
Note
.
Since the program can be written by the user, the
µ
PD75P218 is suitable for preproduction use during
system development, or limited production.
Read this material together with the
µ
PD75218 materials.
Note
Under development
FEATURES
•
•
•
•
•
•
•
µ
PD75218 compatible
On-chip 16K-byte mode/32K-byte mode switching function
Operates at the same power supply voltage range (2.7 to 6.0 V) as the mask ROM version
µ
PD75218.
32640
×
8 bits of PROM
1024
×
4 bits of RAM
No pull-down resistor for Port 6
High breakdown voltage display output
• S0 to S8, T0 to T9 : On-chip pull-down resistor
• S9, T10 to T15
: Open drain
•
No power-on reset circuit
Caution No mask-option pull-down resistor is provided.
ORDERING INFORMATION
Part Number
Package
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14
×
20 mm)
64-pin ceramic LCC with window (14
×
20 mm)
Quality Grade
Standard
Standard
Standard
µ
PD75P218CW
µ
PD75P218GF-3BR
µ
PD75P218KB
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The word “PROM” in this document refers to the common parts of the one-time PROM products and
EPROM products.
The information in this document is subject to change without notice.
Document No. IC-2541A
(O.D. No. IC-7962A)
Date Published
March 1993 P
Printed in Japan
1989
©
NEC CORPORATION 1991
µ
PD75P218
1.
1.1
PIN FUNCTIONS
PORT PINS
Input/
output
Input
I/O
I/O
Input
Input
Shared
pin
INT4
SCK
SO
SI
INT0/V
PP
INT1
INT2
TI0
I/O
–
–
–
BUZ
I/O
MD0 - MD3
Programmable 4-bit I/O port (PORT3).
I/O can be specified bit by bit.
4-bit I/O port (PORT4).
Can directly drive LEDs.
Data input/output pins
for the PROM write and
verify (Four low-order
bits).
P50 - P53
I/O
–
4-bit I/O port (PORT5).
Can directly drive LEDs.
Data input/output pins
for the PROM write and
verify (Four high-order
bits).
P60 - P63
I/O
–
Programmable 4-bit I/O port (PORT6).
I/O can be specified bit by bit.
Suitable for key input.
PH0
PH1
PH2
PH3
Output
T13/S12
T12/S13
T11/S14
T10/S15
4-bit P-ch open drain high breakdown voltage large
current output port (PORTH).
Can directly drive LEDs.
×
High
impedance
×
Input
Input
Input
4-bit I/O port (PORT2).
×
Input
4-bit input port (PORT1).
With noise elimination
function
Input
Function
4-bit input port (PORT0).
8-bit
I/O
×
When reset
Input
Pin name
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30 - P33
P40 - P43
I/O
–
Input
4
µ
PD75P218
1.2
NON-PORT PINS
Input/
output
Shared
pin
–
Note 1
Function
High breakdown voltage large current output pin
for digit output
High breakdown voltage large current output pin
for digit/segment output
The remainder of the pins can be used as PORTH.
High breakdown voltage large current output pin
for digit/segment output
Static output is also available.
High breakdown voltage output pin for segment
output
Static output is also available.
Note 1
High breakdown voltage output pin for segment
output
Low level
When reset
Low level
Pin name
T0 - T9
T10/S15 -
T13/S12
Output
PH3 - PH0
Note 2
High
impedance
T14/S11,
T15/S10
–
S9
S0 - S8
PPO
Output
–
Output for receiving pulse signal for timer/pulse generator
High
impedance
TI0
Input
P13
Input for receiving external event pulse signal for timer/
event counter
SCK
SO
SI
INT4
I/O
I/O
Input
Input
P01
P02
P03
P00
Serial clock I/O
Serial data output or serial data I/O
Serial data input or normal input
Edge detection vectored interrupt input
(either rising edge or falling edge detection)
Edge detection vectored interrupt input with noise elimination
(detection edge selectable)
Edge detection testable input (rising edge detection)
Fixed frequency output pin (for buzzer or system clock trimming)
Crystal/ceramic resonator connection for main system clock
generation.
When external clock is used, it is applied to X1, and its
reserve phase signal is applied to X2.
Input
Input
Input
INT0
INT1
INT2
BUZ
X1, X2
Input
P10/V
PP
P11
Input
I/O
P12
P23
–
Input
XT1, XT2
–
Crystal connection for subsystem clock generation.
When external clock is used, it is applied to XT1, and XT2 is open.
RESET
MD0 - MD3
V
PP
Input
I/O
–
P30 - P33
P10/INT0
System reset input (low level active)
Operation mode selection pins during the PROM write/verify cycles
+12.5 V is applied as the programming voltage during the
PROM write/verify cycles
Pull-down resistor connection pin of FIP
®
controller/driver
Positive power supply. +6 V is applied as the programming
voltage during the PROM write/verify cycles
GND potential
No connection
V
LOAD
V
DD
–
–
V
SS
NC
Note 3
–
–
Note 1.
On-chip pull-down resistor
2.
Open drain output
3.
When using a printed board with a
µ
PD75216A, 75217, or 75218, connect the NC pin to the V
PRE
.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
