DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P3018A
4-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
µ
PD75P3018A replaces the
µ
PD753017A’s internal mask ROM with a one-time PROM, and features expanded
ROM capacity. The
µ
PD75P3018A inherits the function of the
µ
PD75P3018, and enables high-speed operation at
a low supply voltage of 1.8 V.
Because the
µ
PD75P3018A supports programming by users, it is suitable for use in evaluation of systems in
development stages using the
µ
PD753012A, 753016A, or 753017A, and for use in small-scale production.
The following document describes further details of the functions. Please make sure to read this document
before starting design.
µ
PD753017 User’s Manual : U11282E
FEATURES
Compatible with
µ
PD753017A
Memory capacity:
• PROM : 32768
×
8 bits
• RAM
: 1024
×
4 bits
Can operate in the same power supply voltage as the mask version
µ
PD753017A
• V
DD
= 1.8 to 5.5 V
LCD controller/driver
ORDERING INFORMATION
Part Number
Package
80-pin plastic QFP (14
×
14 mm, resin thickness 2.7 mm)
80-pin plastic QFP (14
×
14 mm, resin thickness 1.4 mm)
80-pin plastic TQFP (fine pitch) (12
×
12 mm, resin thickness 1.05 mm)
80-pin plastic TQFP (fine pitch) (12
×
12 mm, resin thickness 1.00 mm)
µ
PD75P3018AGC-3B9
µ
PD75P3018AGC-8BT
µ
PD75P3018AGK-BE9
µ
PD75P3018AGK-9EU
Caution
Mask-option pull-up resistors are not provided in this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U11917EJ2V0DS00 (2nd edition)
Date Published July 2000 N CP (K)
Printed in Japan
The mark
shows major revised points.
©
1997, 2000
µ
PD75P3018A
FUNCTION OUTLINE
Item
Instruction execution time
Function
• 0.95, 1.91, 3.81, 15.3
µ
s (main system clock: at 4.19 MHz operation)
• 0.67, 1.33, 2.67, 10.7
µ
s (main system clock: at 6.0 MHz operation)
• 122
µ
s (subsystem clock: at 32.768 kHz operation)
32768
×
8 bits
1024
×
4 bits
• 4-bit operation: 8
×
4 banks
• 8-bit operation: 4
×
4 banks
8
16
8
8
40
• Segment number selection : 24/28/32 segments (can be changed to CMOS
output port in unit of 4; max. 8)
• Display mode selection
: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias)
1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
5 channels:
• 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter,
carrier generator, timer with gate)
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
• SBI mode
16 bits
•
Φ,
524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)
•
Φ,
750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation)
• 2, 4, 32 kHz
(main system clock: at 4.19 MHz operation
or subsystem clock: at 32.768 kHz operation)
• 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation)
• External : 3
• Internal : 5
• External : 1
• Internal : 1
• Ceramic or crystal oscillator for main system clock oscillation
• Crystal oscillator for subsystem clock oscillation
STOP/HALT mode
V
DD
= 1.8 to 5.5 V
• 80-pin plastic QFP (14
×
14 mm)
• 80-pin plastic TQFP (fine pitch) (12
×
12 mm)
Also used for segment pins
13 V breakdown voltage
On-chip pull-up resistor connection can be specified by using software: 23
Internal memory
PROM
RAM
General-purpose register
Input/output port
CMOS input
CMOS input/output
CMOS output
N-ch open-drain input/output
Total
LCD controller/driver
Timer
Serial interface
Bit sequential buffer (BSB)
Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupt
Test input
System clock oscillator
Standby function
Power supply voltage
Package
2
Data Sheet U11917EJ2V0DS00
µ
PD75P3018A
CONTENTS
1. PIN CONFIGURATION (Top View) ................................................................................................
2. BLOCK DIAGRAM ...........................................................................................................................
3. PIN FUNCTIONS ..............................................................................................................................
3.1
3.2
3.3
3.4
Port Pins ...................................................................................................................................................
Non-port Pins ...........................................................................................................................................
4
5
6
6
8
Pin Input/Output Circuits ......................................................................................................................... 10
Recommended Connection for Unused Pins ........................................................................................ 12
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ....................................... 13
4.1
4.2
Difference between Mk I Mode and Mk II Mode ..................................................................................... 13
Setting of Stack Bank Selection Register (SBS) ................................................................................... 14
5. DIFFERENCES BETWEEN
µ
PD75P3018A AND
µ
PD753012A, 753016A, AND 753017A ....... 15
6. MEMORY CONFIGURATION .......................................................................................................... 16
6.1
6.2
6.3
Program Counter (PC) ............................................................................................................................. 16
Program Memory (PROM) ....................................................................................................................... 16
Data Memory (RAM) ................................................................................................................................. 19
7. INSTRUCTION SET ......................................................................................................................... 20
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ............................................. 30
8.1
8.2
8.3
8.4
Operation Modes for Program Memory Write/Verify ............................................................................ 30
Program Memory Write Procedure ......................................................................................................... 31
Program Memory Read Procedure ......................................................................................................... 32
One-time PROM Screening ..................................................................................................................... 33
9. ELECTRICAL SPECIFICATIONS .................................................................................................... 34
10. PACKAGE DRAWINGS ................................................................................................................... 48
11. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 52
APPENDIX A.
µ
PD75316B, 753017A AND 75P3018A FUNCTION LIST .......................................... 54
APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 56
APPENDIX C. RELATED DOCUMENTS ............................................................................................... 60
Data Sheet U11917EJ2V0DS00
3
µ
PD75P3018A
1. PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14
×
14 mm)
µ
PD75P3018AGC-3B9, 75P3018AGC-8BT
• 80-pin plastic TQFP (fine pitch) (12
×
12 mm)
µ
PD75P3018AGK-BE9, 75P3018AGK-9EU
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
RESET
P73/KR7
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
19
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P60/KR0
X2
X1
V
PP
Note
XT2
XT1
V
DD
P33/MD3
P32/MD2
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P12/INT2/TI1/TI2
P11/INT1
P10/INT0
P03/SI/SB1
Note
Connect the V
PP
directly to V
DD
during normal operation.
PIN IDENTIFICATIONS
BIAS
BP0-BP7
BUZ
COM0-COM3
D0-D7
INT0, 1, 4
INT2
KR0-KR7
LCDCL
MD0-MD3
P00-P03
P10-P13
P20-P23
P30-P33
P40-P43
P50-P53
P60-P63
: LCD Power Supply Bias Control
: Bit Port 0-7
: Buzzer Clock
: Common Output 0-3
: Data Bus 0-7
: External Vectored Interrupt 0, 1, 4
: External Test Input 2
: Key Return 0-7
: LCD Clock
: Mode Selection 0-3
: Port0
: Port1
: Port2
: Port3
: Port4
: Port5
: Port6
P70-P73
PCL
PTO0-PTO2
RESET
S0-S31
SB0, SB1
SCK
SI
SO
SYNC
TI0-TI2
V
DD
V
LC0
-V
LC2
V
PP
Vss
X1, X2
XT1, XT2
: Port7
: Programmable Clock
: Programmable Timer Output 0-2
: Reset
: Segment Output 0-31
: Serial Bus 0,1
: Serial Clock
: Serial Input
: Serial Output
: LCD Synchronization
: Timer Input 0-2
: Positive Power Supply
: LCD Power Supply 0-2
: Programming Power Supply
: Ground
: Main System Clock Oscillation 1, 2
: Subsystem Clock Oscillation 1, 2
4
COM0
COM1
COM2
COM3
BIAS
V
LC0
V
LC1
V
LC2
P40/D0
P41/D1
P42/D2
P43/D3
Vss
P50/D4
P51/D5
P52/D6
P53/D7
P00/INT4
P01/SCK
P02/SO/SB0
Data Sheet U11917EJ2V0DS00
µ
PD75P3018A
2. BLOCK DIAGRAM
PTO1/P21
TIMER/EVENT
COUNTER
#1
INTT1
TIMER/EVENT
COUNTER
#2
INTT2 TOUT0
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
INTBT
PROGRAM
COUNTER
(15)
ALU
SP (8)
CY
SBS
PORT0
4
P00 to P03
TI1/TI2/
P12/INT2
PORT1
4
P10 to P13
PTO2/P22/PCL
PORT2
4
P20 to P23
BANK
PORT3
4
P30/MD0 to
P33/MD3
P40/D0 to
P43/D3
P50/D4 to
P53/D7
PORT4
GENERAL
REG.
PROM
PROGRAM
MEMORY
32768 x 8 BITS
4
PORT5
4
TI0/P13
PTO0/P20
TIMER/EVENT
COUNTER
#0
INTT0 TOUT0
DECODE
AND
CONTROL
PORT6
RAM
DATA
MEMORY
1024 x 4 BITS
4
P60 to P63
BUZ/P23
WATCH
TIMER
INTW f
LCD
PORT7
4
P70 to P73
24
S0 to S23
S24/BP0 to
S31/BP7
COM0 to
COM3
V
LC0
to V
LC2
BIAS
LCDCL/P30/MD0
SYNC/P31/MD1
SI/SB1/P03
SO/SB0/P02
SCK/P01
CLOCKED
SERIAL
INTERFACE
INTCSI TOUT0
LCD
CONTROLLER
/DRIVER
f
LCD
fx/2
N
BIT SEQ.
BUFFER (16)
CPU CLOCK
Φ
SYSTEM CLOCK
CLOCK
CLOCK GENERATOR
STAND BY
OUTPUT
DIVIDER
CONTROL
CONTROL
SUB
MAIN
PCL/PTO2/P22
XT1 XT2 X1 X2
V
DD
8
INT0/P10
INT1/P11
INT2/P12/TI1/TI2
INT4/P00
KR0/P60 to
KR7/P73
8
4
INTERRUPT
CONTROL
3
V
SS
RESET V
PP
Data Sheet U11917EJ2V0DS00
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
