DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P3036
4-BIT SINGLE-CHIP MICROCONTROLLER
The
µ
PD75P3036 replaces the
µ
PD753036’s internal mask ROM with a one-time PROM or EPROM.
Because the
µ
PD75P3036 supports programming by users, it is suitable for use in prototype testing for system
development using the
µ
PD753036 and for use in small-scale production.
*
Caution The
µ
PD75P3036KK-T is not designed to guarantee the reliability required for use in mass-
production. Please use it only for performance evaluation during testing and test production runs.
Detailed descriptions of functions are provided in the following document. Be sure to read the document
before designing.
µ
PD753036 User’s Manual : U10201E
FEATURES
•
Compatible with
µ
PD753036
•
Internal PROM: 16384
×
8 bits
•
µ
PD75P3036KK-T
: Reprogrammable (ideally suited for system evaluation)
•
µ
PD75P3036GC, 75P3036GK : One-time programmable (ideally suited for small-scale production)
•
Internal RAM: 768
×
4 bits
•
Can operate in the same power supply voltage as the mask version
µ
PD753036
• V
DD
= 1.8 to 5.5 V
•
LCD controller/driver
•
A/D converter
Caution
Mask-option pull-up resistors are not provided in this device.
ORDERING INFORMATION
Part Number
Package
80-pin plastic QFP
(14
×
14 mm, 0.65-mm pitch)
80-pin plastic TQFP
(fine pitch) (12
×
12 mm, 0.5-mm pitch)
80-pin ceramic WQFN
Internal PROM
One-time PROM
One-time PROM
EPROM
Quality Grade
Standard
Standard
Not applicable
µ
PD75P3036GC-3B9
µ
PD75P3036GK-BE9
*
µ
PD75P3036KK-T
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice.
Document No. U11575EJ1V0DS00 (1st edition)
(Previous No. IP-3657)
Date Published November 1996 P
Printed in Japan
The mark
*
shows major revised points.
©
1996
µ
PD75P3036
Functional Outline
Parameter
Instruction execution time
Function
• 0.95, 1.91, 3.81, 15.3
µ
s (main system clock: during 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7
µ
s (main system clock: during 6.0-MHz operation)
• 122
µ
s (subsystem clock: during 32.768-kHz operation)
Internal memory
PROM
RAM
General purpose register
16384
×
8 bits
768
×
4 bits
• 4-bit operation: 8
×
4 banks
• 8-bit operation: 4
×
4 banks
8
20
8
8
Also used for segment pins
13 V withstand voltage
On-chip pull-up resistors can be specified by using software: 27
Input/
output
port
CMOS input
CMOS input/output
Bit port output
*
N-ch open-drain
input/output pins
Total
LCD controller/driver
44
• Segment selection:
• Display mode selection:
12/16/20 segments (can be changed to bit port output
in unit of 4; max. 8)
Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),
1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
Timer
5 channels
• 8-bit timer/event counter: 3 channels
(16-bit timer/event counter, carrier generator, timer with gate)
• Basic interval/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
• SBI mode
A/D converter
Bit sequential buffer (BSB)
Clock output (PCL)
8-bit resolution: 8 channels
16 bits
•
Φ,
524, 262, 65.5 kHz (main system clock: during 4.19-MHz operation)
•
Φ,
750, 375, 93.8 kHz (main system clock: during 6.0-MHz operation)
• 2, 4, 32 kHz (main system clock: during 4.19-MHz operation
or subsystem clock: during 32.768-kHz operation)
• 2.86, 5.72, 45.8 kHz (main system clock: during 6.0-MHz operation)
Buzzer output (BUZ)
Vectored interrupt
Test input
System clock oscillator
External: 3, Internal: 5
External: 1, Internal: 1
• Ceramic or crystal oscillator for main system clock oscillation
• Crystal oscillator for subsystem clock oscillation
Standby function
Power supply voltage
Package
STOP/HALT mode
V
DD
= 1.8 to 5.5 V
• 80-pin plastic QFP (14
×
14 mm)
• 80-pin plastic TQFP (fine pitch) (12
×
12 mm)
• 80-pin ceramic WQFN
*
2
µ
PD75P3036
CONTENTS
1. PIN CONFIGURATION (Top View) ............................................................................................... 4
2. BLOCK DIAGRAM ......................................................................................................................... 6
3. PIN FUNCTIONS ............................................................................................................................ 7
3.1
3.2
3.3
3.4
Port Pins ................................................................................................................................................ 7
Non-port Pins ........................................................................................................................................ 9
Pin Input/Output Circuits ...................................................................................................................... 11
Recommended Connection of Unused Pins ...................................................................................... 14
4. Mk I MODE AND Mk II MODE SELECTION FUNCTION .............................................................. 15
4.1
4.2
Difference between Mk I Mode and Mk II Mode .................................................................................. 15
Setting of Stack Bank Selection Register (SBS) ................................................................................ 16
5. DIFFERENCES BETWEEN
µ
PD75P3036 AND
µ
PD753036 ........................................................ 17
6. PROGRAM COUNTER (PC) AND MEMORY MAP ....................................................................... 18
6.1
6.2
6.3
Program Counter (PC) .......................................................................................................................... 18
Program Memory (PROM) .................................................................................................................... 18
Data Memory (RAM) .............................................................................................................................. 20
7. INSTRUCTION SET ....................................................................................................................... 21
8. PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................................. 30
8.1
8.2
8.3
Operation Modes for Program Memory Write/Verify ......................................................................... 30
Program Memory Write Procedure ...................................................................................................... 31
Program Memory Read Procedure ...................................................................................................... 32
*
*
*
*
*
9. PROGRAM ERASURE (
µ
PD75P3036KK-T ONLY) ...................................................................... 33
10. OPAQUE FILM ON ERASURE WINDOW (
µ
PD75P3036KK-T ONLY) ......................................... 33
11. ONE-TIME PROM SCREENING .................................................................................................... 33
12. ELECTRICAL SPECIFICATIONS .................................................................................................. 34
13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ........................................................... 49
14. PACKAGE DRAWINGS ................................................................................................................. 51
15. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 54
APPENDIX A. FUNCTION LIST OF
µ
PD75336, 753036, AND 75P3036 .......................................... 55
APPENDIX B. DEVELOPMENT TOOLS ............................................................................................ 56
APPENDIX C. RELATED DOCUMENTS ............................................................................................ 60
3
µ
PD75P3036
1. PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14
×
14 mm)
µ
PD75P3036GC-3B9
• 80-pin plastic TQFP (fine pitch) (12
×
12 mm)
µ
PD75P3036GK-BE9
• 80-pin ceramic WQFN
µ
PD75P3036KK-T
S31/BP7
S30/BP6
S29/BP5
S28/BP4
S27/BP3
S26/BP2
S25/BP1
S24/BP0
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
P73/KR7
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
RESET
X2
X1
V
PP
XT2
XT1
V
DD
AV
REF
AV
SS
AN5
AN4
AN3
43
19
42
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AN2
AN1
AN0
P83/AN7
P82/AN6
P81/TI2
P80/TI1
P33/MD3
P32/MD2
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
Caution
Connect the V
PP
pin directly to V
DD
.
4
COM0
COM1
COM2
COM3
BIAS
V
LC0
V
LC1
V
LC2
P40/D0
P41/D1
P42/D2
P43/D3
V
SS
P50/D4
P51/D5
P52/D6
P53/D7
P00/INT4
P01/SCK
P02/SO/SB0
µ
PD75P3036
PIN IDENTIFICATIONS
P00 to P03
P10 to P13
P20 to P23
P30 to P33
P40 to P43
P50 to P53
P60 to P63
P70 to P73
P80 to P83
BP0 to BP7
KR0 to KR7
SCK
SI
SO
SB0, SB1
AV
REF
AV
SS
AN0-AN7
MD0 to MD3
D0 to D7
: Port0
: Port1
: Port2
: Port3
: Port4
: Port5
: Port6
: Port7
: Port8
: Bit Port0-7
: Key Return 0-7
: Serial Clock
: Serial Input
: Serial Output
: Serial Bus 0,1
: Analog Reference
: Analog Ground
: Analog Input 0-7
: Mode Selection 0-3
: Data Bus 0-7
S12 to S31
V
LC0
to V
LC2
BIAS
LCDCL
SYNC
TI0 to TI2
PTO0 to PTO2
BUZ
PCL
INT2
X1, X2
XT1, XT2
RESET
V
PP
V
DD
V
SS
: Segment Output 12-31
: LCD Power Supply 0-2
: LCD Power Supply Bias Control
: LCD Clock
: LCD Synchronization
: Timer Input 0-2
: Programmable Timer Output 0-2
: Buzzer Clock
: Programmable Clock
: External Test Input 2
: Main System Clock Oscillation 1, 2
: Subsystem Clock Oscillation 1, 2
: Reset
: Programming Power Supply
: Positive Power Supply
: Ground
COM0 to COM3 : Common Output 0-3
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4
5
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