DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P316B
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The
µ
PD75P316B is a product of the
µ
PD75316B with its built-in ROM having been replaced with the one-
time PROM.
It is most suitable for test production during system development and for production in small amounts since
it can operate under the same supply voltage as mask products.
The one-time PROM product is capable of writing only once and is effective for production of many kinds of
sets in small quantities and early startup.
The EPROM product allows programs to be written and rewritten, making it ideal for system evaluation.
Functions are described in detail in the following User'S Manual, which should be read when carrying out
design work.
µ
PD75308 User's Manual: IEM-5016
FEATURES
•
Compatible (excluding mask option) with the
µ
PD75312B/75316B (mask products)
•
Memory capacity
• Program memory (PROM) : 16256
×
8 bits
• Data memory (RAM)
: 1024
×
4 bits
• Ideal for small set as camera, etc.
ORDERING INFORMATION
Ordering Code
µ
PD75P316BGC-3B9
Package
80-pin plastic QFP (s 14 mm)
s
80-pin plastic QFP (fine pitch) (s 12 mm)
s
80-pin ceramic WQNF (LCC with window)
Internal ROM
One-time PROM
Quality Grade
Standard
µ
PD75P316BGK-BE9
µ
PD75P316BKK-T*
*
Under Development
One-time PROM
Standard
EPROM
Not applicable
(for function evaluation)
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The
µ
PD75P316B EPROM product does not provide a level of reliability suitable for use as a
volume production product for customers' devices. The EPROM product should be used solely for
function evaluation in experiments or preproduction.
In descriptions common to one-time PROM products and EPROM products in this document, the term
"PROM" is used.
The information in this document is subject to change without notice.
Document No. IC-3189
(O.D. No. IC-8696)
Date Published January 1994P
Printed in Japan
The mark
5
shows the major revised points.
© NEC Corporation 1994
µ
PD75P316B
PIN CONFIGURATION (Top View)
s
• 80-pin plastic QFP (s 14 mm)
P73/KR7
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
1
2
3
4
5
6
7
8
9
8079787776 757473 7271 70696867666564636261
S1
S0
RESET
s
• 80-pin plastic TQFP (fine pitch)(s 12 mm)
• 80-pin ceramic WQFN (LCC with window)
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P60/KR0
X2
X1
V
PP
*
XT2
XT1
V
DD
P33/MD3
P32/MD2
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
P22/PCL
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
µ
PD75P316BGC-3B9
µ
PD75P316BGK-BE9
µ
PD75P316BKK-T
10
11
12
13
14
15
16
17
18
19
20
2122232425 262728 2930 31323334353637383940
P53
P00/INT4
*
In normal operation, V
PP
input should be the V
DD
level.
P00-03
P10-13
P20-23
P30-33
P40-43
P50-53
P60-63
P70-73
BP0-7
KR0-7
SCK
SI
SO
SB0, 1
RESET
S0-31
COM0-3
: Port 0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Port
Port
Port
Port
1
2
3
4
V
LC0-2
BIAS
LCDCL
SYNC
TI0
PTO0
BUZ
PCL
INT0, 1, 4
INT2
X1, 2
XT1, 2
MD0-3
V
DD
V
SS
V
PP
: LCD Power Supply 0-2
:
:
:
:
:
:
:
:
:
:
:
:
LCD Power Supply Bias Control
LCD Clock
LCD Synchronization
Timer Input 0
Programmable Timer Output 0
Buzzer Clock
Programmable Clock
External Vectored Interrupt 0, 1, 4
External Test Input 2
Main System Clock Oscillation 1, 2
Subsystem Clock Oscillation 1, 2
Mode Selection
Port 5
Port 6
Port 7
Bit Port
Key Return
Serial Clock
Serial Input
Serial Output
Serial Bus 0, 1
Reset Input
Segment Output 0-31
Common Output 0-3
: Positive Power Supply
: Ground
: Programing/Verifying Power
2
P01/SCK
P02/SO/SB0
COM3
BIAS
V
LC0
V
LC1
V
LC2
COM0
COM1
COM2
P41
P42
P43
V
SS
P40
P50
P51
P52
BLOCK DIAGRAM
BASIC
INTERVAL
TIMER
PORT0
4
P00-P03
INTBT
PROGRAM
COUNTER (14)
SP(8)
CY
ALU
PORT2
PORT1
4
P10-P13
TI0/P13
PTO0/P20
BANK
PORT4
PORT3
4
P20-P23
TIMER/EVENT
COUNTER
#0
INTT0
4
P30-P33
/MD0-MD3
P40-P43
4
BUZ/P23
PROGRAM
MEMORY
(PROM)
DECODE
AND
CONTROL
DATA
MEMORY
(RAM)
1024
×
4 BITS
GENERAL REG.
PORT5
WATCH
TIMER
4
P50-P53
INTW
f
LCD
m
16256
×
8 BITS
PORT6
4
P60-P63
SI/SB1/P03
SO/SB0/P02
SCK/P01
SERIAL BUS
INTERFACE
PORT7
4
P70-P73
INTCSI
24
8
4
3
CPU
CLOCK
f
LCD
S0-S23
S24/BP0
–S31/BP7
COM0–COM3
V
LC0
–V
LC2
BIAS
LCDCL/P30
SYNC/P31
INT0/P10
INT1/P11
INT2/P12
INTERRUPT
CONTROL
INT4/P00
KR0/P60
–KR7/P73
8
f
X
/ 2
N
BIT SEQ.
BUFFER (16)
SYSTEM CLOCK
CLOCK
CLOCK
GENERATOR STAND BY
OUTPUT
DIVIDER
SUB MAIN CONTROL
CONTROL
PCL/P22
XT1 XT2 X1 X2
LCD
CONTROL-
LER
/DRIVER
µ
PD75P316B
V
PP
V
DD
V
SS
RESET
3
µ
PD75P316B
CONTENTS
1.
PIN FUNCTIONS .........................................................................................................................................
5
1.1
1.2
1.3
PORT PINS ........................................................................................................................................................... 5
OTHER PINS ......................................................................................................................................................... 7
PIN INPUT/OUTPUT CIRCUITS ......................................................................................................................... 9
2.
3.
4.
DIFFERENCES BETWEEN PRODUCTS IN SERIES ................................................................................
11
DATA MEMORY (RAM) ............................................................................................................................
12
PROGRAM MEMORY WRITE AND VERIFY ............................................................................................
14
4.1
4.2
4.3
4.4
PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ....................................................................... 14
PROGRAM MEMORY WRITING PROCEDURE ............................................................................................... 15
PROGRAM MEMORY READING PROCEDURE ............................................................................................... 16
ERASURE PROCEDURE(
µ
PD75P316BKK-T-ONLY) ........................................................................................ 17
5.
6.
7.
ELECTRICAL SPECIFICATIONS ...............................................................................................................
18
PACKAGE INFORMATION .......................................................................................................................
39
RECOMMENDED SOLDERING CONDITIONS ........................................................................................
42
APPENDIX A. DEVELOPMENT TOOLS .........................................................................................................
43
APPENDIX B. RELATED DOCUMENTS ........................................................................................................
44
4
µ
PD75P316B
1. PIN FUNCTIONS
1.1
PORT PINS (1/2)
Pin Name
P00
P01
P02
P03
P10
P11
Input
P12
P13
P20
P21
Input/output
P22
P23
P30
*2
P31
*2
Input/output
P32
*2
P33
*2
MD2
MD3
N-ch open-drain 4-bit input/output port (PORT
4).
Data input/output pins for program memory
(PROM) write/verify (low-order 4 bits).
PCL
BUZ
LCDCL
SYNC
MD0
MD1
Programmable 4-bit input/output port (PORT3)
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
×
INT2
TI0
PTO0
—
4-bit input/output port (PORT2)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
×
Input/Output
Input
Input/output
Input/output
Input/output
Dual-Function
Pin
INT4
SCK
SO/SB0
SI/SB1
INT0
INT1
With noise elimination circuit
4-bit input port (PORT1)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
×
4-bit input port (PORT0)
Internal pull-up resistor specification by
software is possible for P01 to P03 as a 3-bit
unit.
×
Function
8-bit I/O
Afer Reset
I/O Circuit
Type*1
B
F -A
Input
F -B
M-C
Input
B -C
Input
E-B
Input
E-B
P40 to P43*2
Input/output
—
High impedance
M-A
P50 to P53
*2
Input/output
—
N-ch open-drain 4-bit input/output port (PORT
5)
Data input/output pins for program memory
(PROM) write/verify (high-order 4 bits).
High impedance
M-A
P60
P61
P62
P63
P70
P71
P72
P73
Input/output
Input/output
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
4-bit input/output port (PORT7).
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
Programmable 4-bit input/output port (PORT6).
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
Input
F -A
Input
F -A
* 1.
2
.
: Indicates a Schmitt-triggered input.
Direct LED drive capability.
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
