DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P3116
4-BIT SINGLE-CHIP MICROCONTROLLER
The
µ
PD75P3116 replaces the
µ
PD753108’s internal mask ROM with a one-time PROM, and features expanded ROM
capacity.
Because the
µ
PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the
development stage using the
µ
PD753104, 753106, or 753108, and for use in small-scale production.
Detailed information about functions is provided in the following User’s Manual. Be sure to read it before
designing:
µ
PD753108 User’s Manual : U10890E
FEATURES
Compatible with
µ
PD753108
Memory capacity:
• PROM : 16384 x 8 bits
• RAM
: 512 x 4 bits
Can be operated in same power supply voltage range as the mask version
µ
PD753108
• V
DD
= 1.8 to 5.5 V
On-chip LCD controller/driver
QTOP
TM
microcontroller
Remark
QTOP microcontrollers are microcontrollers with on-chip one-time PROM that are totally supported by NEC.
The support include writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part Number
Package
64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
µ
PD75P3116GC-AB8
µ
PD75P3116GK-8A8
Caution This device does not provide an internal pull-up resistor connection function by means of mask
option.
The information in this document is subject to change without notice.
Document No. U11369EJ2V0DS00 (2nd edition)
Date Published March 1997 N
Printed in Japan
The mark
shows major revised points.
©
1994
µ
PD75P3116
FUNCTION OUTLINE
Item
Instruction execution time
Function
• 0.95, 1.91, 3.81, or 15.3
µ
s (main system clock: @ 4.19 MHz)
• 0.67, 1.33, 2.67, or 10.7
µ
s (main system clock: @ 6.0 MHz)
• 122
µ
s (subsystem clock: @ 32.768 kHz)
16384 x 8 bits
512 x 4 bits
• 4-bit manipulation: 8 x 4 banks
• 8-bit manipulation: 4 x 4 banks
8
20
4
32
• Segment number selection : 16/20/24 segments (Switchable to CMOS I/O
ports in a batch of 4 pins, max. 8 pins)
• Display mode selection
: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),
1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
5 channels: • 8-bit timer/event counter : 3 channels
(Can be used as 16-bit timer/event counter, carrier generator,
and timer with gate)
• Basic interval timer/watchdog timer : 1 channel
• Watch timer : 1 channel
• 3-wire serial I/O mode ··· MSB/LSB first switchable
• 2-wire serial I/O mode
• SBI mode
16 bits
Φ,
524, 262, and 65.5 kHz (main system clock: @ 4.19 MHz)
Φ,
750, 375, and 93.8 kHz (main system clock: @ 6.0 MHz)
• 2, 4, and 32 kHz (main system clock: @ 4.19 MHz or subsystem clock: @ 32.768 kHz)
• 2.93, 5.86, 46.9 kHz (main system clock: @ 6.0 MHz)
• External : 3
• Internal : 5
• External : 1
• Internal : 1
• Ceramic/crystal oscillation circuit for main system clock
• Crystal oscillation circuit for subsystem clock
STOP/HALT mode
V
DD
= 1.8 to 5.5 V
• 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
Internal pull-up resistor connection can be specified by software: 7
Internal pull-up resistor connection can be specified by software: 12
Shared by segment pin: 8
13-V withstand voltage
Internal memory
PROM
RAM
General-purpose register
I/O ports
CMOS input
CMOS I/O
N-ch open-drain I/O
Total
LCD controller/driver
Timers
Serial interface
Bit sequential buffer (BSB)
Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupts
Test inputs
System clock oscillation circuit
Standby function
Power supply voltage
Package
2
µ
PD75P3116
CONTENTS
1. PIN CONFIGURATION (Top View) ..................................................................................................
2. BLOCK DIAGRAM ............................................................................................................................
3. PIN FUNCTIONS ...............................................................................................................................
3.1
3.2
3.3
3.4
Port Pins ...................................................................................................................................................
Non-port Pins ...........................................................................................................................................
4
5
6
6
8
Equivalent Circuits for Pins .................................................................................................................... 10
Recommended Connection of Unused Pins ......................................................................................... 12
4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................. 13
4.1
4.2
Differences between Mk I Mode and Mk II Mode ................................................................................... 13
Setting of Stack Bank Selection (SBS) Register ................................................................................... 14
5. DIFFERENCES BETWEEN
µ
PD75P3116 AND
µ
PD753104, 753106, AND 753108 ...................... 15
6. MEMORY CONFIGURATION ........................................................................................................... 16
7. INSTRUCTION SET .......................................................................................................................... 18
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 27
8.1
8.2
8.3
8.4
Operation Modes for Program Memory Write/Verify ............................................................................ 27
Program Memory Write Procedure ......................................................................................................... 28
Program Memory Read Procedure ......................................................................................................... 29
One-time PROM Screening ..................................................................................................................... 30
9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 31
10. CHARACTERISTIC CURVES (REFERENCE VALUES) .................................................................. 46
11. PACKAGE DRAWINGS ................................................................................................................... 48
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50
APPENDIX A. FUNCTION LIST OF
µ
PD75308B, 753108, AND 75P3116 ........................................... 51
APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 53
APPENDIX C. RELATED DOCUMENTS ............................................................................................... 57
3
µ
PD75P3116
1. PIN CONFIGURATION (Top View)
• 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) :
µ
PD75P3116GC-AB8
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) :
µ
PD75P3116GK-8A8
COM3
COM2
COM1
COM0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BIAS
V
LC0
V
LC1
V
LC2
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2
P33/MD3
Vss
P50/D4
P51/D5
P52/D6
P53/D7
P60/KR0/D0
P61/KR1/D1
P62/KR2/D2
S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
Note
Always connect the V
PP
pin directly to V
DD
during normal operation.
PIN IDENTIFICATIONS
P00-P03
P10-P13
P20-P23
P30-P33
P50-P53
P60-P63
P80-P83
P90-P93
KR0-KR3
SCK
SI
SO
SB0, SB1
RESET
MD0 to MD3
D0 to D7
S0 to S23
: Port0
: Port1
: Port2
: Port3
: Port5
: Port6
: Port8
: Port9
: Key Return 0 to 3
: Serial Clock
: Serial Input
: Serial Output
: Serial Data Bus 0, 1
: Reset
: Mode Selection 0 to 3
: Data Bus 0 to 7
: Segment Output 0 to 23
COM0 to COM3 : Common Output 0 to 3
V
LC0
to V
LC2
BIAS
LCDCL
SYNC
TI0 to TI2
PTO0 to PTO2
BUZ
PCL
INT0, 1, 4
INT2
X1, X2
XT1, XT2
V
PP
V
DD
Vss
: LCD Power Supply 0 to 2
: LCD Power Supply Bias Control
: LCD Clock
: LCD Synchronization
: Timer Input 0 to 2
: Programmable Timer Output 0 to 2
: Buzzer Clock
: Programmable Clock
: External Vectored Interrupt 0, 1, 4
: External Test Input 2
: Main System Clock Oscillation 1, 2
: Subsystem Clock Oscillation 1, 2
: Programming Power Supply
: Positive Power Supply
: Ground
4
P63/KR3/D3
RESET
XT1
XT2
V
PP
Note
X1
X2
V
DD
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P10/INT0
P11/INT1
P12/INT2/TI1/TI2
P13/TI0
µ
PD75P3116
2. BLOCK DIAGRAM
BUZ/P23
WATCH
TIMER
INTW f
LCD
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
INTBT
PROGRAM
COUNTER (14)
ALU
SP (8)
CY
SBS
PORT0
4
P00 to P03
PORT1
4
P10 to P13
PORT2
4
P20 to P23
P30/MD0 to
P33/MD3
P50/D4 to
P53/D7
P60/D0 to
P63/D3
P80 to P83
BANK
PORT3
4
TI0/P13
PTO0/P20
8-BIT
TIMER/EVENT
COUNTER #0
GENERAL
REG.
PROGRAM
MEMORY
(PROM)
16384 x 8 BITS
PORT5
4
TI1/TI2/
P12/INT2
PTO1/P21
PTO2/
PCL/P22
TOUT0
INTT0 TOUT0
INTT1
8-BIT
CASCADED
TIMER/EVENT 16-BIT
COUNTER #1 TIMER/
EVENT
8-BIT
TIMER/EVENT COUNTER
COUNTER #2
INTT2
CLOCKED
SERIAL
INTERFACE
INTCSI TOUT0
INT1
INTERRUPT
CONTROL
4
BIT SEQ.
BUFFER (16)
PORT6
4
DECODE
AND
CONTROL
PORT8
DATA
MEMORY
(RAM)
512 x 4 BITS
4
PORT9
4
P90 to P93
SI/SB1/P03
SO/SB0/P02
SCK/P01
16
S0 to S15
S16/P93 to
S19/P90
S20/P83 to
S23/P80
COM0 to COM3
BIAS
V
LC0
V
LC1
V
LC2
SYNC/P31
LCDCL/P30
4
LCD
CONTROLLER/
DRIVER
INT0/P10
INT1/P11
INT4/P00
INT2/P12/TI1/TI2
P60/KR0 to
P63/KR3
4
fx/2
N
CPU CLOCK
Φ
f
LCD
4
SYSTEM CLOCK
CLOCK
CLOCK GENERATOR
STAND BY
OUTPUT
DIVIDER
CONTROL
CONTROL
MAIN
SUB
PCL/PTO2/P22
X1 X2 XT1 XT2
V
DD
Vss V
PP
RESET
5
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