DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD77018A, 77019
16 bits, Fixed-point Digital Signal Processor
µ
PD77018A, 77019 are 16 bits fixed-point DSPs (Digital Signal Processors) developed for digital signal processing
with its demand for high speed and precision.
Maximum operating speed of the
µ
PD77018A, 77019 is improved compared with the
µ
PD77015, 77017, 77018.
And the
µ
PD77019 internal instruction RAM (4K
×
32 bits) is suitable for program code replacement.
FEATURES
•
FUNCTIONS
• Instruction cycle: 16.6 ns (MIN.)
Operation clock: 60 MHz
External clock: 60, 30, 20, 15, 7.5 MHz
Crystal: 60 MHz
• On-chip PLL to provide higher operation clock than the external clock
• Dual load/store
• Hardware loop function
• Conditional execution
• Executes product-sum operation in one instruction cycle
•
PROGRAMMING
• 16 bits
×
16 bits + 40 bits
→
40 bits multiply accumulator
• 8 general registers (40 bits each)
• 8 ROM/RAM data pointer: each data memory area has 4 registers
• 10 source interrupts (external: 4, internal: 6)
• 3 operand instructions (example: R0 = R0 +R1L∗R2L)
• Nonpipeline on execution stage
•
MEMORY AREAS
• Instruction memory area : 64K words
×
32 bits
• Data memory areas : 64K words
×
16 bits
×
2 (X memory, Y memory)
In this document, all descriptions of the
µ
PD77018A also apply to the
µ
PD77019, unless otherwise
specified.
The information in this document is subject to change without notice.
Document No. U11849EJ2V0DS00 (2nd edition)
Date Published October 1997 N
Printed in Japan
The mark
shows major revised points.
©
1996
µ
PD77018A, 77019
•
CLOCK GENERATOR
• Mask option for CLKOUT pin:
Fixed to the low level.
Does not output the internal system clock.
• Selectable source clock: external clock input and crystal resonator
[External clock]
On-chip PLL to provide higher operation clock (60 MHz max.) than the external clock.
Variable multiple rates (1, 2, 3, 4, 8) by mask option.
[Crystal resonator]
Oscillation frequency corresponds directly to the system clock frequency (Sure to specify the mask option
frequency multiple as "1").
•
ON-CHIP PERIPHERAL
• I/O port: 4 bits
• Serial I/O (16 bits): 2 channels
• Host I/O (8 bits): 1 channel
•
CMOS
•
+3 V single power supply
ORDERING INFORMATION
Part Number
Package
100-pin plastic TQFP (FINE PITCH) (14
×
14 mm)
100-pin plastic TQFP (FINE PITCH) (14
×
14 mm)
µ
PD77018AGC-×××-9EU
µ
PD77019GC-×××-9EU
Remark
×××
indicates a code suffix.
2
Functional Differences among the
µ
PD7701× Family
µ
PD77016
µ
PD77015
µ
PD77017
µ
PD77018
µ
PD77018A
µ
PD77019
4K words
24K words
None
1K words each
2K words each
16K words each
30 ns (33 MHz)
16.6 ns (60 MHz)
4K words each
12K words each
2K words each
3K words each
256 words
4K words
12K words
1.5K words
None
48K words
2K words each
None
48K words each
Item
Internal instruction RAM
Internal instruction ROM
External instruction memory
Data RAM (X/Y memory)
Data ROM (X/Y memory)
External data memory
Instruction cycle
(Maximum operation speed)
66 MHz
33/16.5/8.25/4.125 MHz
Variable multiple rate (1, 2, 4, 8 ) by mask option.
External clock
(at maximum operation speed)
60/30/20/15/7.5 MHz
Variable multiple rate (1, 2, 3, 4, 8 ) by
mask option.
60 MHz
Crystal
(at maximum operation speed)
–
33 MHz
–
Channel 1 has the
same functions
as channel 2.
5V
160-pin plastic QFP
Instruction
STOP instruction is added.
Channel 1 has the same functions as that of the
µ
PD77016.
Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection).
3V
100-pin plastic TQFP
Serial interface (2 Channels)
Power supply
Package
µ
PD77018A, 77019
5
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