DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD7759
ADPCM SPEECH SYNTHESIZER LSIs
The
µ
PD7759 is an external ROM type speech synthesis LSI employing the waveform coding
method. In addition to the ROM capability of up to 1 Mbit, the
µ
PD7759 realizes the synthesis of
speech sounds of any length by using the ADPCM data transferred from an external ROM.
As the synthesizing method, it adopts the ADPCM method and the PCM + waveform element method.
The ADPCM method is suitable for synthesizing clear and natural speech sounds, and the PCM + waveform
element method is for the synthesis of sound effects and melodies. And by using them together, the
µ
PD7759 realizes the long-time synthesis of high-quality sounds.
Because of the short turn-around time of speech analysis, the
µ
PD7759 can perform the quick system
development using a PROM, or the evaluation of an on-chip ROM type of the
µ
PD7755 family.
FEATURES
5
q
Synthesizing method
q
Sampling frequency
q
Bit rate (speech)
q
Number of Messages
5
q
External speech data ROM
Parameters
Speech data ROM
(External)
Products
Speech (ADPCM)
50 sec. (TYP.)
Synthesizing time
Note1
: ADPCM, PCM + waveform element methods used together
: 5, 6 or 8 kHz
: 20 to 32 K bps
: 256 (MAX.)
Melodies & sound effects
Note2
(PCM + waveform element)
340 sec. (TYP.)
µ
PD7759
1 Mbits
Note 1.
The synthesizing time for the speech is the value for a 6 kHz sampling.
2.
The synthesizing time for the melodies & sound effects is variable according to their tone.
q
Speech output
q
Host CPU interface
q
Standby mode
q
Supply voltage
q
CMOS technology
: Current sink type analog output, 9-bit D/A converter
: Compatible with a 4/8-bit CPU
: Pop-noise preventive circuit incorporated
: 2.7 to 5.5 V
ORDERING INFORMATION
Part Number
Package
40-pin plastic DIP (600 mil)
52-pin plastic QFP (s 14 mm)
s
Quality grade
Standard
Standard
µ
PD7759C
µ
PD7759GC-3BH
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No. IC-2323A
(O.D.No.
IC-6960D)
Date Published January 1993
Printed in Japan
The mark
5
shows revised points.
©
1988, 1993
µ
PD7759
PIN CONFIGURATION (Top View)
•
40-pin plastic DIP
ASD5
ASD6
ASD7
I0
I1
I2
I3
I4
I5
I6
I7
AEN/ WR
SAA
DRQ
ALE
REF
AVO
BUSY
RESET
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
ASD4
ASD3
ASD2
ASD1
ASD0
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
X2
X1
ST
MD
•
52-pin plastic QFP
NC
CS
X2
X1
ST
MD
NC
GND
RESET
BUSY
AVO
REF
NC
NC
A0
A1
A2
A3
A4
NC
A5
A6
A7
A8
ASD0
NC
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
25
42
24
43
23
44
22
45
21
46
20
µ
PD7759GC-3BH
47
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
NC
ALE
DRQ
SAA
AEN / W R
I7
NC
I6
I5
I4
I3
I2
NC
BLOCK DIAGRAM
ASD0 to ASD7
A0 to A8
NC
ASD1
ASD2
ASD3
ASD4
V
DD
NC
ASD5
ASD6
ASD7
I0
I1
NC
µ
PD7759C
SAA
ALE
DRQ
MD
BUSY
CS
ST
X1
ROM Address & Speech Data Interface
OSC
X2
REF
AEN/ WR
System
Controller
ADPCM
Decoder
D/A
Converter
AVO
RESET
V
DD
GND
Message Select Interface
I0 to I7
2
µ
PD7759
1. PIN FUNCTIONS
1.1 COMMON FUNCTION TO ALL MODES
Pin
(Abbre-
viation)
V
DD
DRQ
52-pin
QFP
Pin No.
6
24
40-pin
DIP
Pin No.
40
14
—
Output
Power supply (2.7 to 5.5 V)
Speech synthesis data request.
D/A converter reference current input.
The sink-load current input causes the output current of the
REF
28
16
Input
D/A converter to change.
The D/A converter reference current is passed to V
DD
via
a resistor.
In standby mode, REF is set to high impedance.
Analog speech signal output.
AVO outputs a unipolar sink-load current.
The output current is reduced to 0 when the
µ
PD7759 is in the
AVO
29
17
Output
standby mode.
The output current of the D/A converter from AVO is changed
according to the input current from REF.
Maximum output current of the D/A converter is approx. the
34 times the REF input current.
Active-low BUSY signal output. When inputting ST signal,
BUSY
30
18
Output
it outputs a low level signal.
MD, ST and WR are invalid while BUSY is low.
In standby mode, BUSY is set to high impedance.
Reset input.
In standby mode, RESET must be at low level more than 12
RESET
31
19
Input
clock cycles after clock oscillation becomes stable.
In operation mode, RESET must be at low level for 12 clock
cycles (oscillation clock).
GND
32
20
—
Ground.
Ceramic resonator connection for generating a clock signal.
The 640 kHz ceramic resonator can be connected.
In standby mode, the
µ
PD7759 outputs a low-level to X1 and
X2
37
24
—
a high-level to X2.
I/O
Function
5
X1
36
23
—
1, 7, 13,
NC
14, 20, 26,
27, 33, 39,
40, 46, 52
—
—
No Connection
3
µ
PD7759
1.2 PIN FUNCTION FOR STAND ALONE MODE
Pin
(Abbre-
viation)
I0
I1
I2
I3
I4
I5
I6
I7
52-pin
QFP
Pin No.
11
12
15
16
17
18
19
21
40-pin
DIP
Pin No.
4
5
6
7
8
9
10
11
Output/
Input
Input
Message selection code input.
The message selection code signals are positive logics.
Ground the pins not used.
These pins are connected to the internal latch circuit which
latches I0 to I7 data at the rising edge of the ST input.
In standby mode, these pins should be set high or low level.
If they are biased at or near the typical CMOS threshold,
the excess supply current is caused.
This signal is at low level while address signal is valid.
Controls the latch circuit for the higher 8 bits of the external
ROM address.
Outputs high level when the start address of a message stored
in the directory area of data memory, is being read out.
Determines the timing that higher 8 bits of the external ROM
ALE
25
15
Output
address are externally latched. They must be latched at the
falling edge of the signal.
MD
34
21
Input
set at high-level.
Start signal input.
When ST goes low while CS is at low level, the
µ
PD7759 starts
ST
35
22
Input
synthesizing the message specified by I0 to I7. In standby
mode, this signal resets the standby mode and starts speech
synthesis.
Chip select signal input.
CS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ASD0
ASD1
ASD2
ASD3
ASD4
ASD5
ASD6
ASD7
38
41
42
43
44
45
47
48
49
50
51
2
3
4
5
8
9
10
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1
2
3
Input/
Output
(1) Outputs the higher 8 bits of external ROM address.
(2) Inputs 8-bit speech synthesis data from the external ROM.
These functions are executed from (1) to (2) on a time-
shared basis.
Output
Outputs the lower 9 bits of the external ROM address.
Input
ST becomes valid when CS goes low.
I/O
Function
AEN/WR
22
12
SAA
23
13
Output
4
µ
PD7759
1.3 PIN FUNCTION FOR SLAVE MODE
Pin
(Abbre-
viation)
I0
I1
I2
I3
I4
I5
I6
I7
52-pin
QFP
Pin No.
11
12
15
16
17
18
19
21
40-pin
DIP
Pin No.
4
5
6
7
8
9
10
11
Output/
AEN/WR
22
12
Input
Inputs write strobe signal for a speech synthesis data.
Input
Invalid.
Set at high or low level.
I/O
Function
Invalid.
SAA
23
13
Output
Leave this pin open.
Invalid.
ALE
25
15
Output
Leave this pin open.
Slave mode selection input.
MD
34
21
Input
Transition between two operation mode is not accepted
during synthesis or in the standby mode.
Invalid.
ST
35
22
Input
Set at high level.
Chip select signal input.
CS
38
25
Input
WR becomes valid when CS goes low.
A0
A1
A2
A3
A4
A5
A6
A7
A8
ASD0
ASD1
ASD2
ASD3
ASD4
ASD5
ASD6
ASD7
41
42
43
44
45
47
48
49
50
51
2
3
4
5
8
9
10
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1
2
3
Input
Input speech synthesis data from an external source.
Output
Invalid.
Leave these pins open.
5
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