SPANSION
Data Sheet
TM
Flash Memory
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices
and Fujitsu. Although the document is marked with the name of the company that originally developed the spec-
ification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
TM
product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20870-6E
FLASH MEMORY
CMOS
8M (1M
×
8) BIT
MBM29LV080A
-70/90
■
DESCRIPTION
The MBM29LV080A is a 16 M-bit, 3.0 V-only Flash memory organized as 1 M bytes of 8 bits each. The 1 M bytes
of data is divided into 32 sectors of 64 K bytes of flexible erase capability. The 8 bits of data will appear on
DQ
0
to DQ
7
. The MBM29LV080A is offered in a 40-pin TSOP (I) package. The device is designed to be programmed
in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase
operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV080A offers access times of 70 ns and 90 ns, allowing operation of high-speed micro-
processors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable
(WE), and output enable (OE) controls.
(Continued)
■
PRODUCT LINE UP
MBM29LV080A
-70
Power Supply Voltage V
CC
(V)
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
3.3 V
+0.3 V
–0.3 V
-90
3.0 V
+0.6 V
–0.3 V
70
70
30
90
90
35
■
PACKAGES
40-pin plastic TSOP (I)
Marking Side
40-pin plastic TSOP (I)
Marking Side
(FPT-40P-M06)
(FPT-40P-M07)
MBM29LV080A
-70/90
(Continued)
The MBM29LV080A is pin and command set compatible with JEDEC standard E
2
PROMs. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV080A is programmed by executing the program command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and
verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase
is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies
proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV080A is erased when shipped from the factory.
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a mom-busy sector. Thus, true background erase can be achieved.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
The MBM29LV080A also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read
mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV080A memory electrically erases all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte at a time using
the EPROM programming mechanism of hot electron injection.
2
MBM29LV080A
-70/90
■
FEATURES
•
Address specification is not necessary during command sequence
•
Single 3.0 V read, program and erase
Minimizes system level power requirements
•
Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
•
Compatible with JEDEC-standard world-wide pinouts
40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)
•
Minimum 100,000 program/erase cycles
•
High performance
70 ns maximum access time
•
Sector erase architecture
16 sectors of 64 K bytes each
Any combination of sectors can be concurrently erased. MBM29LV080A also supports full chip erase.
•
Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
•
Embedded Program
TM
* Algorithms
Automatically programs and verifies data at specified address
•
Data polling and toggle bit feature for detection of program or erase cycle completion
•
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
•
Low V
CC
write inhibit
≤
2.5 V
•
Hardware RESET pin
Resets internal state machine to the read mode
•
Erase suspend/resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
•
Sector protection
Hardware method disables any combination of sectors from program or erase operations
•
Sector protection set function by extended sector protect command
•
Temporary sector unprotection
Temporary sector unprotection via the RESET pin
*: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
3
MBM29LV080A
-70/90
■
PIN ASSIGNMENTS
TSOP (I)
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE
RESET
N.C.
RY/BY
A
18
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
(Marking Side)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
17
V
SS
N.C.
A
19
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
V
CC
N.C.
DQ
3
DQ
2
DQ
1
DQ
0
OE
V
SS
CE
A
0
Normal Bend
FPT-40P-M06
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
18
RY/BY
N.C.
RESET
WE
A
8
A
9
A
11
A
12
A
13
A
14
A
15
A
16
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
Reverse Bend
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A
0
CE
V
SS
OE
DQ
0
DQ
1
DQ
2
DQ
3
N.C.
V
CC
V
CC
DQ
4
DQ
5
DQ
6
DQ
7
A
10
A
19
N.C.
V
SS
A
17
FPT-40P-M07
4
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