FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
ICS844031-01
G
ENERAL
D
ESCRIPTION
The ICS844031-01 is an Ethernet Clock Generator
and a member of the HiPerClocks
TM
family of high
HiPerClockS™
performance devices from IDT. The ICS844031-01
uses an 18pF parallel resonant crystal over the
range of 19.6MHz - 27.2MHz. For Ether net
applications, a 25MHz crystal is used to generate 312.5MHz.
The ICS844031-01 has excellent <1ps phase jitter performance,
over the 1.875MHz - 20MHz integration range. The ICS844031-
01 is packaged in a small 8-pin TSSOP, making it ideal for use
in systems with limited board space.
F
EATURES
•
One differential LVDS output
•
Crystal oscillator interface, 18pF parallel resonant crystal
(19.6MHz - 27.2MHz)
•
Output frequency range: 245MHz - 340MHz
•
VCO range: 490MHz - 680MHz
•
RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.53ps (typical)
•
3.3V or 2.5V operating supply
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
C
OMMON
C
ONFIGURATION
T
ABLE
Inputs
Crystal Frequency (MHz)
25
M
25
N
2
Multiplication
Value M/N
12.5
Output Frequency
(MHz)
312.5
B
LOCK
D
IAGRAM
OE
Pullup
P
IN
A
SSIGNMENT
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
nQ
OE
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
N = ÷2
(fixed)
Q
nQ
ICS844031-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
M = ÷25
(fixed)
IDT
™
/ ICS
™
LVDS CLOCK GENERATOR
1
ICS844031BG-01 REV. A MAY 1, 2008
ICS844031-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT, XTAL_IN
OE
nQ, Q
V
DD
Power
Power
Input
Input
Output
Power
Pullup
Type
Description
Analog supply pin.
Power supply ground.
Cr ystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Output enable pin. When HIGH, Q/nQ output is active.
When LOW, the Q/nQ output is in a high impedance state.
LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
Core supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
IDT
™
/ ICS
™
LVDS CLOCK GENERATOR
2
ICS844031BG-01 REV. A MAY 1, 2008
ICS844031-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
Package Thermal Impedance,
θ
JA
129.5°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
tended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
Typical
3.3
3.3
Maximum
3.465
V
DD
75
10
Units
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.10
Typical
2.5
2.5
Maximum
2.625
V
DD
70
10
Units
V
V
mA
mA
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
OE
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
T
ABLE
3D. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.15
1.33
Test Conditions
Minimum
275
Typical
Maximum
425
50
1.45
50
Units
mV
mV
V
mV
NOTE: Please refer to Parameter Measurement Information for output information.
IDT
™
/ ICS
™
LVDS CLOCK GENERATOR
3
ICS844031BG-01 REV. A MAY 1, 2008
ICS844031-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
T
ABLE
3E. LVDS DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.05
1.26
Test Conditions
Minimum
215
Typical
Maximum
430
50
1.45
50
Units
mV
mV
V
mV
NOTE: Please refer to Parameter Measurement Information for output information.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
19.6
Test Conditions
Minimum
Typical
Fundamental
27.2
50
7
MHz
Ω
pF
Maximum
Units
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
312.5MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
Minimum
245
0.53
200
48
400
52
Typical
Maximum
340
Units
MHz
ps
ps
%
t
jit(Ø)
t
R
/ t
F
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
312.5MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
Minimum
245
0.68
200
48
400
52
Typical
Maximum
340
Units
MHz
ps
ps
%
t
jit(Ø)
t
R
/ t
F
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
IDT
™
/ ICS
™
LVDS CLOCK GENERATOR
4
ICS844031BG-01 REV. A MAY 1, 2008
ICS844031-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
T
YPICAL
P
HASE
N
OISE AT
312.5MH
Z
@ 3.3V
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.53ps (typical)
➤
Ethernet Filter
312.5MHz
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
312.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.68ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
312.5MH
Z
@ 2.5V
➤
Ethernet Filter
➤
Phase Noise Result by adding
an Ethernet Filter to raw data
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
IDT
™
/ ICS
™
LVDS CLOCK GENERATOR
5
➤
Phase Noise Result by adding
an Ethernet Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
ICS844031BG-01 REV. A MAY 1, 2008
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
