DS3F Device
DS3 Framer
TXC-03401B
DATA SHEET
FEATURES
• DS3 payload access, bit-serial or nibble-parallel
• C-bit parity or M13 operating mode
• C-bit interface (13 C-bits in, 14 out)
• Detect and generate DS3 AIS, and idle signals
• Transmit reference generator for serial operation
• Transmit and receive Far End Alarm and Control
(FEAC) with double word capability and automatic
transmission
• Maskable hardware interrupt for eight alarms
• Transmit single errors: framing, FEBE, C-bit parity,
and P-bit parity
• FEBE, C-bit, and P-bit performance counters
• Counters for F-bit and M-bit errors
• Counter for coding violations and excessive zeros
• Transmit-to-Receive and Receive-to-Transmit
loopbacks
• Outputs can be set to high-impedance state
• Selectable mode for TXC-03401 emulation
• Single +5 volt power supply
• Available as 68-pin plastic leaded chip carrier or
80-pin thin plastic quad flat package (TQFP)
DESCRIPTION
The DS3F is designed for DS3 framer applications in
which broadband payloads are mapped into the 44.736
Mbit/s DS3 frame format. Although the C-bit parity for-
mat is recommended, the DS3F can also operate in the
M13 mode. In the C-bit parity format, the DS3F provides
a separate interface for selected C-bits. The DS3F also
provides for transmitting and receiving the FEAC chan-
nel and Blue code AIS conditions, and generates and
detects DS3 AIS, DS3 idle, P-bit parity and C-bit parity.
In addition, performance counters are provided, as well
as the ability to generate single framing, FEBE, C-bit
parity and P-bit parity errors. The device also provides
X-bit inversion, receive loop timing and indications for
FEAC idle channel, FEAC word stack overflow and
Severely Errored Frame. The payload interface is select-
able through software as either a bit-serial or nibble-par-
allel format.
APPLICATIONS
• Subrate multiplexing
• Wideband data or video transport
• DS3 monitor and test
• Channel extenders
• DS3 test sets
LINE SIDE
+5V
TERMINAL SIDE
Serial/nibble
clock, data &
frame output
Transmit DS3
reference generator
output
Serial/nibble
clock, data &
frame input
DS3F
DS3 NRZ I/O
clock & data
DS3 Framer
TXC-03401B
C-bits I/O
DS3 stuff bits
clocks & data
Microprocessor clock & data
interface
Transmit errors
Copyright
2001 TranSwitch Corporation
TranSwitch and TXC and are registered trademarks of TranSwitch Corporation
Document Number:
TXC-03401B-MB
Ed. 6, June 2001
TranSwitch Corporation
•
3 Enterprise Drive
•
Shelton, Connecticut 06484
Tel: 203-929-8810
•
Fax: 203-926-9453
•
www.transwitch.com
•
USA
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
DS3F
TXC-03401B
TABLE OF CONTENTS
Section
Page
List of Figures ....................................................................................................................................2
Block Diagram ...................................................................................................................................3
Block Diagram Description ................................................................................................................4
Pin Diagrams .....................................................................................................................................6
Pin Descriptions .................................................................................................................................8
Absolute Maximum Ratings and Environmental Limitations ............................................................17
Thermal Characteristics ...................................................................................................................17
Power Requirements .......................................................................................................................17
Input, Output And Input/Output Parameters ....................................................................................18
Timing Characteristics .....................................................................................................................20
Operation .........................................................................................................................................32
Power, Ground And External Components ..............................................................................32
Throughput Delays ...................................................................................................................32
Memory Map ....................................................................................................................................33
Memory Map Descriptions ...............................................................................................................34
Package Information ........................................................................................................................45
Ordering Information ........................................................................................................................47
Related Products .............................................................................................................................47
Standards Documentation Sources .................................................................................................48
List of Data Sheet Changes .............................................................................................................50
Documentation Update Registration Form*
................................................................................53
* Please note that TranSwitch provides documentation for all of its products. Current editions of many documents are
available from the Products page of the TranSwitch Web site at www.transwitch.com. Customers who are using a
TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive relevant
updated and supplemental documentation as it is issued. They should also contact the Applications Engineering
Department to ensure that they are provided with the latest available information about the product, especially before
undertaking development of new designs incorporating the product.
LIST OF FIGURES
Figure
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Page
DS3F TXC-03401B Block Diagram .........................................................................................3
DS3F TXC-03401B 68-Pin PLCC Pin Diagram .......................................................................6
DS3F TXC-03401B 80-Pin TQFP Pin Diagram .......................................................................7
Line Side DS3 Receive Input Timing .....................................................................................20
Line Side DS3 Transmit Output Timing .................................................................................21
Terminal Side Receive Nibble Output Timing ........................................................................21
Terminal Side Transmit Nibble Input Timing .........................................................................22
Terminal Side Receive Serial Output Timing .........................................................................23
Terminal Side Transmit Serial Input Timing ..........................................................................24
C-Bit Transmit Input Timing ...................................................................................................25
C-Bit Receive Output Timing .................................................................................................26
Transmit Reference Generator Timing ..................................................................................27
Force Error Timing (C-Bit Parity, P-Bit Parity, FEBE) ............................................................28
Force Overhead Bit Error Timing ...........................................................................................28
Stuff Opportunity Bit Timing (M13 Mode) ..............................................................................29
Microprocessor Read Cycle ..................................................................................................30
Microprocessor Write Cycle ...................................................................................................31
Power Supply Connections ...................................................................................................32
DS3F TXC-03401B 68-Pin Plastic Leaded Chip Carrier .......................................................45
DS3F TXC-03401B 80-Pin Thin Profile Plastic Quad Flat Package ......................................46
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TXC-03401B-MB
Ed. 6, June 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
DS3F
TXC-03401B
BLOCK DIAGRAM
LINE SIDE
X1
X2
FE
D3RD
D3RC
CRD
CRCK
CRF
CRDCC
STUFC
STUFD/HINT
TERMINAL SIDE
Receive
Serial
Parallel
RNIB3
RNIB2
RNIB1
RNIB0
RCN
N.C.
RFN
DS3 Frame
Alignment
DS3
Interpreter
Output
RNIB3
N.C.
N.C.
RDS
RCS
RCG
RFS
AD(7-0)
WR
RD
ALE
SEL
OENA
FORCEOE
CXD
CXCK
CXF
CXDCC
D3TD
D3TC
FORCECP/CVCNT
FORCEPP/EXZCNT
FORCEFEBE
µP
I/O
RT Payload
Loopback
Transmit
Frame
Reference
Generator
TDOUT
TCG
TFOUT
TCOUT
TFIN
TCIN
N.C.
XSC
XCK
XFSI
XDS
N.C.
N.C.
N.C.
XFNO
XNC
XCK
N.C.
XNIB3
XNIB2
XNIB1
XNIB0
Input
DS3
Send
Transmit
Note: N.C. indicates No Connection.
Figure 1. DS3F TXC-03401B Block Diagram
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TXC-03401B-MB
Ed. 6, June 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
DS3F
TXC-03401B
BLOCK DIAGRAM DESCRIPTION
Figure 1 shows the block diagram of the DS3F device.
The DS3F is designed to operate in both "Normal" (N) and "Extended-features" (E) modes of operation. In the
Normal mode, the device emulates the TranSwitch TXC-03401 DS3F device. In the Extended-features mode,
all the additional capabilities described in this Data Sheet are available. Technical Bulletin TB-511 describes
the differences between the TXC-03401 and the TXC-03401B (document number TXC-03401-TB1). Either
mode of operation can be selected by setting control bit EMODE in the memory map. Two input pins
(FORCECP/CVCNT and FORCEPP/EXZCNT) and one output pin (STUFD/HINT) can change their functions
according to the mode selected (N/E). Memory map addresses above 07H are effective only in the Extended-
features mode.
The DS3F receives a line side DS3 data signal (D3RD) and a clock signal (D3RC) from a line interface device
such as the TranSwitch ART/ARTE VLSI device (TXC-02020/02021) or DS3LIM-SN module (TXC-20153D or
TXC-20153G). The DS3 Frame Alignment Block performs DS3 frame alignment that will not lock to a false
framing pattern. There are internal 8-bit F- and M-bit error counters included in the Extended-features mode of
the framer to monitor errors. The DS3F also monitors the signal and the input clock for loss of signal (LOS), out
of frame (OOF), and loss of clock (LOC). A framing error (FE) output is provided to indicate when any of the 31
framing bits in the DS3 signal are in error.
The DS3 Interpreter Block performs P-bit and C-bit parity detection and error counting, receive AIS and idle
pattern detection, far end block error (FEBE) detection and error counting, far end alarm and control (FEAC)
code word detection of up to 4 different types, C-bit reception and X-bit reception. Serial interfaces are pro-
vided for the received X-bits and for 14 of the 21 C-bits. In the Extended-features mode, groups of the C-bits
can be set by writing to the memory map. The receive C-bit interface consists of a serial data signal (CRD),
clock signal (CRCK), framing pulse (CRF), and a data communication link clock signal (CRDCC). The clock
signal (CRCK) is gapped and is available only for clocking out C-bits C2 through C6, and C13 through C21.
The CRDCC clock signal is present only for C-bits C13, C14 and C15, which are assigned as a data communi-
cation channel when operating in the C-bit parity mode. In the Extended-features mode, the timing of the
CRDCC receive clock edges can be reversed by setting a control bit in the memory map.
When operating in the M13 mode, an interface (output pin STUFD) that indicates the state of the stuff opportu-
nity bit during each of the seven DS3 subframes and a clock signal (STUFC) are also provided. The Stuff Data
Status (STUFD) output pin is shared with the Hardware Interrupt (HINT) pin for the Extended-features mode.
The Hardware Interrupt output is used to the inform the microprocessor that a severe alarm condition has
occurred. The polarity of the Hardware Interrupt output is selectable by a control bit to meet the requirements
of the microprocessor's interrupt input pin. When a hardware interrupt does occur, it can be isolated to one of
up to up to eight different latched alarm types if they are enabled in the memory map.
The Output Block provides a bit-serial or a nibble-parallel interface for C-bit parity mode. The M13 mode uses
the bit-serial interface only. Note that since the sum of the payload and C-bits in a DS3 frame is not evenly
divisible by four, M13 nibble mode operation is not feasible. The interface type is selected by writing to a control
bit in the memory map (SER), and is common to the DS3F receive and transmit circuitry. The signals provided
for the bit-serial interface consist of a data signal (RDS), a clock signal (RCS), a receive clock gap signal
(RCG) and framing pulse (RFS). The nibble-parallel interface consists of the nibble data signal (RNIB3 through
RNIB0), a clock out signal (RCN), and a framing pulse output (RFN). The RNIB3 bit corresponds to the first bit
received in a four-bit serial bit stream segment.
In the transmit direction, the Input Block provides either a bit-serial or nibble-parallel interface. The bit-serial
interface consists of a data signal (XDS), clock signals (XCK and optionally XSC), and a framing pulse (XFSI).
The nibble-parallel interface consists of the nibble data (XNIB3 through XNIB0), a clock out signal (XCK), a
framing pulse (XFNO), and a nibble clock signal (XNC). The XNIB3 bit corresponds to the first bit transmitted.
The DS3 Send Block performs P-bit and C-bit parity generation, AIS and idle pattern generation, far end alarm
and control (single or double FEAC word) transmission, X-bit insertion, and C-bit insertion. For C-bit Parity
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TXC-03401B-MB
Ed. 6, June 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
DS3F
TXC-03401B
mode, the C-bits may be generated internally (such as C-bit parity), written by the microprocessor (such as the
FEAC channel), or provided from the external C-bit interface. In C-bit Parity mode, the C1 bit is always trans-
mitted as a 1. The transmit C-bit interface consists of a data input signal (CXD), a clock signal (CXCK), a fram-
ing pulse (CXF) and a data communication link clock (CXDCC). For M13 mode, all of the C-bits are input from
the terminal side’s bit-serial interface. The DS3 transmit line side interface consists of the data signal (D3TD)
and a clock signal (D3TC).
DS3F transmit-to-receive (TR) loopback is controlled by setting a bit in the memory map (3LOOP). The entire
device is used when loopback is in effect, but the line side input data and clock are blocked (by the gate pre-
ceding the DS3 Frame Alignment Block shown in Figure 1). In the Extended-features mode of operation, a
receive-to-transmit payload (RTP) loopback is also available by use of control bit RTPLOOP
.
The capability to generate and transmit single overhead bit errors is also provided. External interfaces are pro-
vided for transmitting a far end block error (FORCEFEBE), a P-bit parity error (FORCEPP), a C-bit parity error
(FORCECP) and an overhead bit error (FORCEOE). The FORCEOE signal is used in conjunction with the
enable signal (OENA) for introducing an overhead bit error in the next 85-bit segment of the DS3 frame. When
the Extended-features mode (EMODE), Coding Violation Enable (CVEN) and Excessive Zeros Enable
(EXZEN) control bits in the memory map are set to 1, the Coding Violations Count (CVCNT) function and
Excessive Zeros Count (EXZCNT) functions pin replace the FORCECP and FORCEPP functions, respectively.
The purpose of these pins is to utilize the DS3F's 16-bit counter CVEXZ to count coding violation and/or exces-
sive zeros events. Indications of these events are provided to the DS3F by TranSwitch's ART or ARTE devices
(TXC-02020/02021). The ART's CV output pin indicates both coding violations and excessive zeros. Therefore,
only the CVCNT input pin to the DS3F is required to count both types of event. When the ARTE is used in con-
junction with the DS3F, there are separate CV and EXZ inputs available to the DS3F, which can be or-gated
together in the DS3F's 16-bit counter, if required. The DS3F has an internal 16-bit shadow counter incorpo-
rated into its counter design. This prevents CV or EXZ counts being lost during a read cycle.
The Transmit Frame Reference Generator Block provides reference timing for bit-serial operation. This block
accepts an external 44.736MHz clock signal (TCIN) and derives a clock signal (TCOUT), a framing pulse
(TFOUT), a clock gap signal (TCG) and a data signal (TDOUT). The DS3 data signal consists of framing bits
and zeros elsewhere. An optional input framing pulse (TFIN) is also provided, but is not required for normal
operation.
The DS3F microprocessor bus interface consists of eight bidirectional data and address pins (AD0-AD7),
along with other microprocessor control pins. The microprocessor bus is used to write control information and
to read status information and alarms. When operating in the Extended-features mode the DS3F memory map
contains twenty-one effective addresses (00H-14H), compared with eight (00H-07H) in the Normal mode.
When the DS3F is operating in the Extended-features mode, its many additional features may be activated via
control bits in the memory map. These features include: ability to tri-state all output ports, X-bit inversion,
receive loop timing, receive and transmit Blue Code AIS conditions, FEAC Idle Channel Indication, a receive
FEAC FIFO stack overflow bit, a Severely Errored Frame indication, and double FEAC word handling.
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TXC-03401B-MB
Ed. 6, June 2001
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