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IDT54/74FCT652T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL
TRANSCEIVER/
REGISTER (3-STATE)
IDT54/74FCT652T/AT/CT
FEATURES:
−
−
−
−
−
−
−
−
−
Low input and output leakage
≤1µ
A (max.)
CMOS power levels
True TTL input and output compatibility
•
V
OH
= 3.3V (typ.)
•
V
OL
= 0.3V (typ.)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Std., A, and C speed grades
High drive outputs (-15mA I
OH
, 64mA I
OL
)
Power off disable outputs permit “live insertion”
Available in the following packages:
•
Industrial: SOIC, SSOP, QSOP
•
Military: CERDIP, LCC, CERPACK
DESCRIPTION:
The FCT652T consists of a bus transceiver with 3-state D-type flip-flops
and control circuitry arranged for multiplexed transmission of data directly
from the data bus or from the internal storage registers. The FCT652T
utilizes GAB and
GBA
signals to control the transceiver functions.
SAB and SBA control pins are provided to select either real- time or stored
data transfer. The circuitry used for select control will eliminate the typical
decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. A low input level selects real-time data and a high
selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock pins (CPAB or
CPBA), regardless of the select or enable control pins.
FUNCTIONAL BLOCK DIAGRAM
GBA
GAB
CPB A
SBA
CPA B
SAB
B REG
ONE OF EIGHT CHANNELS
1D
C1
A1
A REG
1D
C1
B1
TO SEVEN OTHE R CHANNELS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
c
1999 Integrated Device Technology, Inc.
AUGUST 2000
DSC-5508/-
IDT54/74FCT652T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
CPAB
CPBA
27
GAB
SAB
GAB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
GND
2
3
4
5
6
7
8
9
10
11
12
D24-1
SO24-2
SO24-7
SO24-8
E24-1
23
22
21
20
19
18
17
16
15
14
13
CPBA
SBA
GBA
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
A
1
A
2
A
3
NC
A
4
A
5
A
6
5
6
7
8
9
10
11
12
13
14
15
16
17
18
L28-1
4
3
2
1
28
26
25
24
23
22
21
20
19
NC
INDEX
Vcc
CPAB
1
V
CC
SBA
24
SAB
GBA
B
1
B
2
NC
B
3
B
4
B
5
A
8
A
7
B
8
B
7
GND
CERDIP/ SOIC/ SSOP/ QSOP/ CERPACK
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
Rating
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max.
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
8T-link
PIN DESCRIPTION
Pin Names
A
1
- A
8
B
1
- B
8
CPAB, CPBA
SAB, SBA
GAB,
GBA
Description
Data Register A Inputs
Data Register B Outputs
Data Register B Inputs
Data Register A Outputs
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
No
terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
8T-link
NOTE:
1. This parameter is measured at characterization but not tested.
2
NC
B
6
IDT54/74FCT652T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE
(2)
Inputs
GAB
L
L
X
H
L
L
L
L
H
H
H
GBA
H
H
H
H
X
L
L
L
H
H
L
CPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
CPBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
SAB
X
X
X
X
X
X
X
X
L
H
H
SBA
X
X
X
X
X
X
L
H
X
X
H
A
1
- A
8
Input
Input
Input
Unspecified
(1)
Output
Output
Input
Output
Data I/O
B
1
- B
8
Input
Unspecified
(1)
Output
Input
Input
Input
Output
Output
Operation or Function
Isolation
Store A and B Data
Store A, Hold B
Store A in Both Registers
Hold A, Store B
Store B in Both Registers
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and Stored B Data to A Bus
NOTES:
1. The data output functions may be enabled or disabled by various signals at the GAB or
GBA
inputs. Data input functions are always enabled, i.e. data
at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
2. H = HIGH
L = LOW
X = Don't Care
↑
= LOW-to-HIGH transition.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
3
IDT54/74FCT652T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
BUS
A
BUS
B
BUS
A
BUS
B
GAB
L
GBA
L
CPAB
X
CPBA
X
SAB
X
SBA
L
GAB
H
GBA
H
CPAB
X
CPBA
X
SAB
L
SBA
X
REAL-TIME TRANSFER
BUS B TO A
REAL-TIME TRANSFER
BUS A TO B
BUS
A
BUS
B
BUS
A
BUS
B
GAB
X
L
L
GBA
H
X
H
CPAB
↑
CPBA
X
↑
↑
SAB
X
X
X
SBA
X
X
X
GAB
H
GBA
L
CPAB
H or L
CPBA
H or L
SAB
H
SBA
H
X
↑
STORAGE FROM
A AND/OR B
TRANSFER STORES
DATA TO A AND/OR B
4
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