DATA SHEET
MOS INTEGRATED CIRCUIT
m
PD78042F, 78043F, 78044F, 78045F
8-BIT SINGLE-CHIP MICROCOMPUTER
The
m
PD78042F,
m
PD78043F,
m
PD78044F, and
m
PD78045F are 8-bit single-chip microcomputers that incorpo-
rate many hardware peripherals such as an FIP
®
controller/driver, 8-bit resolution A/D converter, timer, serial
interface, and interrupt controller.
The one-time PROM and EPROM models that can operate in the same voltage range as that of masked ROM
models, and various development tools are provided.
The functions of these microcomputers are described in detail in the following User’s Manual. Be sure
to read this manual when you design a system using any of these microcomputers.
m
PD78044F Sub-Series User’s Manual : U10908E
78K/0 Series User's Manual, Instruction: IEU-1372
FEATURES
•
High-capacity ROM and RAM
Item
Product name
Program memory
(ROM)
16K bytes
24K bytes
32K bytes
40K bytes
1024 bytes
Data memory
Internal high-speed RAM
512 bytes
Buffer RAM
64 bytes
FIP display RAM
48 bytes
m
PD78042F
m
PD78043F
m
PD78044F
m
PD78045F
•
Wide range of instruction execution time - from
high-speed (0.4
m
s) to ultra low-speed (122
m
s)
•
I/O ports: 68
•
FIP controller/driver: total display outputs: 34
APPLICATIONS
•
•
•
•
8-bit resolution A/D converter: 8 channels
Serial interface: 2 channels
Timer: 6 channels
Power supply voltage: V
DD
= 2.7 to 5.5 V
5
CD players, cassete tape recorders, tuners, minicomponent stereos, VCRs, microwave ovens, ECRs, etc.
ORDERING INFORMATION
Part number
Package
80-pin plastic QFP (14
¥
20 mm)
80-pin plastic QFP (14
¥
20 mm)
80-pin plastic QFP (14
¥
20 mm)
80-pin plastic QFP (14
¥
20 mm)
m
PD78042FGF-¥¥¥-3B9
m
PD78043FGF-¥¥¥-3B9
m
PD78044FGF-¥¥¥-3B9
m
PD78045FGF-¥¥¥-3B9
Remark
¥¥¥
indicates ROM code number.
The information in this document is subject to change without notice.
Document No. U10700EJ1V0DS00 (1st edition)
Date Published July 1996 P
Printed in Japan
The mark
5
shows major revised points.
©
1996
1990
m
PD78042F, 78043F, 78044F, 78045F
5
78K/0 SERIES PRODUCT DEVELOPMENT
The 78K/0 series products were developed as shown below. The sub-series names are indicated in frames.
For control
100-pin
100-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
42/44-pin
Products under
mass production
Products under
development
2
The Y Subseries is compatible with the I C bus.
µ
PD78078
µ
PD78070A
µ
PD78058F
µ
PD78054
µ
PD78018F
µ
PD78014
µ
PD780001
µ
PD78002
µ
PD78083
For FIP driving
µ
PD78078Y
µ
PD78070AY
µ
PD78058FY
µ
PD78054Y
µ
PD78018FY
µ
PD78014Y
µ
PD78002Y
A timer added to the
µ
PD78054 and external interface functions enhanced.
ROM-less product of the
µ
PD78078
Counter-measure against EMI noise added to the
µ
PD78054
An UART and D/A converter added to the
µ
PD78014 and I/O
function enhanced.
Low-voltage (1.8 V) versions of the
µ
PD78014. ROM and RAM variations
enhanced.
An A/D converter and 16-bit timer added to the
µ
PD78002.
An A/D converter added to the
µ
PD78002
Basic subseries for control
These products include an UART and can operate at a low voltage (1.8 V).
The I/O and FIP C/D of the
µ
PD78044F enhanced.
Total indication output pins: 53
A 6-bit U/D counter added to the
µ
PD78024.
Total indication output pins: 34
Basic subseries for FIP driving. Total indication output pins: 26
78K/0
series
100-pin
80-pin
64-pin
µ
PD780208
µ
PD78044F
µ
PD78024
For LCD driving
100-pin
100-pin
100-pin
µ
PD780308
µ
PD78064B
µ
PD78064
µ
PD780308Y
µ
PD78064Y
SIO of the
µ
PD78064 enhanced and ROM/RAM expanded.
Counter-measure against EMI noise added to the
µ
PD78064.
Basic subseries for LCD driving. These products include an UART.
Compatible with IEBus
TM
80-pin
µ
PD78098
For LV
An IEBus controller added to the
µ
PD78054.
100-pin
µ
PD78P0914
PWM output, LV digital code decoder, built-in Hsync counter.
2
m
PD78042F, 78043F, 78044F, 78045F
The table below shows the main differences between subseries.
Function
Subseries name
For control
ROM
capacity
32K-60K
–
48K-60K
16K-60K
8K-60K
8K-32K
8K
8K-16K
8K-16K
32K-60K
16K-40K
24K-32K
48K-60K
32K
16K-32K
32K-60K
2ch
1ch
1ch
1ch
8ch
2ch
3ch (UART : 1ch)
69 pins
2.7 V
2ch
1ch
1ch
1ch
8ch
–
3ch (UART : 1ch)
2ch (UART : 1ch)
2ch
1ch
–
–
1ch
–
1ch
1ch
–
8ch
8ch
–
1ch (UART : 1ch)
2ch
1ch
39 pins
53 pins
33 pins
74 pins
68 pins
54 pins
57 pins
1.8 V
2.0 V
–
1.8 V
2.7 V
–
–
–
2ch
53 pins
2ch
Timer
8-bit 16-bit Watch WDT
4ch
1ch
1ch
1ch
8-bit
A/D
8ch
8-bit
D/A
2ch
Serial
interface
3ch (UART : 1ch)
V
DD
Min. External
value expansion
1.8 V
2.7 V
I/O
88 pins
61 pins
69 pins
m
PD78078
m
PD78070A
m
PD78058F
m
PD78054
m
PD78018F
m
PD78014
m
PD780001
m
PD78002
m
PD78083
5
2.0 V
1.8 V
2.7 V
–
For FIP
driving
m
PD780208
m
PD78044F
m
PD78024
For LCD
driving
m
PD780308
m
PD78064B
m
PD78064
5
Compatible
with IEBus
For LV
m
PD78098
m
PD78P0914
32K
6ch
–
–
1ch
8ch
–
2ch
54 pins
4.5 V
5
3
m
PD78042F, 78043F, 78044F, 78045F
FUNCTIONAL OUTLINE
Product name
Item
Internal
memory
ROM
Internal high-speed RAM
Buffer RAM
FIP display RAM
General registers
Instruction
cycle
For main system clock
For subsystem clock
Instruction set
m
PD78042F
16K bytes
512 bytes
64 bytes
48 bytes
m
PD78043F
24K bytes
m
PD78044F
32K bytes
1024 bytes
m
PD78045F
40K bytes
8 bits
¥
32 registers (8 bits
¥
8 registers
¥
4 banks)
Variable instruction execution time
0.4
m
s/0.8
m
s/1.6
m
s/3.2
m
s/6.4
m
s (at 5.0 MHz)
122
m
s (at 32.768 kHz)
• Multiplication/division (8 bits
¥
8 bits, 16 bits ÷ 8 bits)
• Bit (set, reset, test, Boolean algebra)
I/O ports (including those
multiplexed with FIP pins)
Total
• CMOS input
• CMOS I/O
• N-ch open-drain
• P-ch open-drain I/O
• P-ch open-drain output
: 68 lines
:
2 lines
: 27 lines
:
5 lines
: 16 lines
: 18 lines
FIP controller/driver
Total
• Segments
• Digits
: 34 lines
: 9 to 24 lines
: 2 to 16 lines
A/D converter
• 8-bit resolution
¥
8 channels
• Power supply voltage: AV
DD
= 4.0 to 5.5 V
5
Serial interface
• 3-wire serial I/O/SBI/2-wire serial I/O selectable modes: 1 channel
• 3-wire serial I/O mode (with automatic transmission/
reception function of up to 64 bytes)
: 1 channel
: 1 channel
: 2 channels
: 1 channel
: 1 channel
: 1 channel
Timer
• 16-bit timer/event counter
• 8-bit timer/event counter
• Watch timer
• Watchdog timer
• 6 bit up/down counter
Timer output
Clock output
3 lines (one for 14-bit PWM output)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(Main system clock: at 5.0 MHz)
32.768 kHz (Subsystem clock: at 32.768 kHz)
Buzzer output
Vectored
interrupt
Maskable interrupt
Non-maskable interrupt
Software interrupt
Text input
1.2 kHz, 2.4 kHz, 4.9 kHz (Main system clock: at 5.0 MHz)
Internal 10 lines, external 4 lines
Internal 1 line
1 line
Internal 1 line
V
DD
= 2.7 to 5.5 V
80-pin plastic QFP (14
¥
20 mm)
5
Power supply voltage
Package
4
m
PD78042F, 78043F, 78044F, 78045F
CONTENTS
1.
2.
3.
PIN CONFIGURATION (TOP VIEW) ........................................................................................
BLOCK DIAGRAM .....................................................................................................................
PINS FUNCTIONS .....................................................................................................................
3.1
3.2
3.3
PORT PINS ......................................................................................................................................
PINS OTHER THAN PORT PINS ...................................................................................................
PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ........................................................
6
8
9
9
11
13
4.
5.
MEMORY SPACE ......................................................................................................................
PERIPHERAL HARDWARE FUNCTIONS ...............................................................................
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
PORTS .............................................................................................................................................
CLOCK GENERATOR CIRCUIT ....................................................................................................
TIMER/EVENT COUNTER ..............................................................................................................
CLOCK OUTPUT CONTROL CIRCUIT .........................................................................................
BUZZER OUTPUT CONTROL CIRCUIT .......................................................................................
A/D CONVERTER ...........................................................................................................................
SERIAL INTERFACE ......................................................................................................................
FIP CONTROLLER/DRIVER ..........................................................................................................
16
17
17
18
18
21
21
22
22
24
6.
INTERRUPT FUNCTION AND TEST FUNCTION ....................................................................
6.1
6.2
INTERRUPT FUNCTION.................................................................................................................
TEST FUNCTION ............................................................................................................................
26
26
29
7.
8.
9.
STANDBY FUNCTION ...............................................................................................................
RESET FUNCTION ....................................................................................................................
INSTRUCTION SET ...................................................................................................................
30
30
31
34
58
63
64
65
67
5
5
5
10. ELECTRICAL SPECIFICATIONS .............................................................................................
11. CHARACTERISTIC CURVE (REFERENCE VALUE) ..............................................................
12. PACKAGE DRAWING ...............................................................................................................
13. RECOMMENDED SOLDERING CONDITIONS ........................................................................
APPENDIX A DEVELOPMENT TOOLS .........................................................................................
APPENDIX B RELATED DOCUMENTS .........................................................................................
5
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