DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD78044H, 78045H, 78046H
8-BIT SINGLE-CHIP MICROCOMPUTER
The
µ
PD78044H,
µ
PD78045H, and
µ
PD78046H are
µ
PD78044H sub-series products in the 78K/0 series.
These microcomputers are advanced models of the
µ
PD78044A sub-series, featuring the added N-ch open-drain
I/O ports.
In addition, the
µ
PD78P048B (one-time PROM or EPROM model) that can operate in the same voltage range as
that of the mask ROM models, and various development tools are provided.
The functions of these microcomputers are described in detail in the following User’s Manual. Be sure
to read this manual when you design a system using any of these microcomputers.
µ
PD78044H Sub-Series User’s Manual : To be created
78K/0 Series User's Manual, Instruction: IEU-1372
FEATURES
• I/O ports: 68 (N-ch open-drain I/O: 13)
• High-capacity ROM and RAM
Item
Product name
Program memory
(ROM)
32K bytes
40K bytes
48K bytes
Data memory
Internal high-speed RAM
1024 bytes
FIP display RAM
48 bytes
µ
PD78044H
µ
PD78045H
µ
PD78046H
• Wide range of instruction execution time:
From high-speed (0.4
µ
s) to ultra low-speed (122
µ
s)
• FIP controller/driver: total display outputs: 34
• 8-bit resolution A/D converter: 8 channels
• Serial interface: 1 channel
• Timer: 5 channels
• Power supply voltage: V
DD
= 2.7 to 5.5 V
APPLICATIONS
VCRs, audio systems, etc.
ORDERING INFORMATION
Part number
Package
80-pin plastic QFP (14
×
20 mm)
80-pin plastic QFP (14
×
20 mm)
80-pin plastic QFP (14
×
20 mm)
µ
PD78044HGF-×××-3B9
µ
PD78045HGF-×××-3B9
µ
PD78046HGF-×××-3B9
Remark
×××
indicates ROM code number.
The information in this document is subject to change without notice.
Document No. U10865EJ1V0DS00 (1st edition)
Date Published August 1996 P
Printed in Japan
The mark
5
shows major revised points.
©
1990
1996
µ
PD78044H, 78045H, 78046H
78K/0 SERIES PRODUCT DEVELOPMENT
The 78K/0 series products were developed as shown below. The sub-series names are indicated in frames.
Products being mass-produced
Products under development
Y sub-series products are compatible with the I
2
C bus.
Used for control
100-pin
100-pin
100-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
42-/44-pin
µ
PD78078
µ
PD78070A
µ
PD780018
µ
PD78058F
µ
PD78054
µ
PD78018F
µ
PD78014
µ
PD780001
µ
PD78002
µ
PD78083
For FIP driving
µ
PD78078Y
µ
PD78070AY
µ
PD780018Y
µ
PD78058FY
µ
PD78054Y
µ
PD78018FY
µ
PD78014Y
µ
PD78002Y
A timer has been added to the
µ
PD78054 to enhance external interface functions.
ROM-less versions of the
µ
PD78078
The serial I/O of the
µ
PD78078 has been enhanced. The functions have been
limited.
EMI noise-reduced version of the
µ
PD78054
An UART and D/A converter have been added to the
µ
PD78014 to enhance I/O.
Low-voltage (1.8 V) versions of the
µ
PD78014. ROM and RAM variations have
been enhanced.
An A/D converter and 16-bit timer have been added to the
µ
PD78002.
An A/D converter has been added to the
µ
PD78002.
Basic sub-series for control
These products include an UART and can operate at a low voltage (1.8 V).
100-pin
80-pin
78K/0
series
80-pin
64-pin
µ
PD780208
µ
PD78044F
µ
PD78044H
µ
PD78024
For LCD driving
The I/O and FIP C/D of the
µ
PD78044F have been enhanced.
Total indication output pins: 53
A 6-bit U/D counter has been added to the
µ
PD78024.
Total indication output pins: 34
N-ch open-drain I/O ports have been added to the
µ
PD78044F.
Total indication output pins: 34
Basic sub-series for FIP driving. Total indication output pins: 26
100-pin
100-pin
100-pin
µ
PD780308
µ
PD78064B
µ
PD78064
µ
PD780308Y
µ
PD78064Y
The SIO of the
µ
PD78064 has been enhanced. ROM and RAM
have been expanded.
EMI noise-reduced version of the
µ
PD78064
Sub-series for LCD driving. These products include an UART.
Compatible with IEBus
TM
80-pin
µ
PD78098
For LV
An IEBus controller has been added to the
µ
PD78054.
64-pin
µ
PD78P0914
A PWM output, LV digital code decoder, and Hsync counter are
incorporated.
2
µ
PD78044H, 78045H, 78046H
The table below shows the main differences between sub-series.
Timer
8-bit 16-bit Watch WDT
4ch
1ch
1ch
1ch
Function
Sub-series name
ROM
capacity
32K-60K
—
48K-60K
48K-60K
16K-60K
8K-60K
8K-32K
8K
8K-16K
8-bit
A/D
8ch
8-bit
D/A
2ch
Serial
interface
3ch (UART:1ch)
I/O
Minimum
V
DD
1.8 V
2.7 V
External
expan-
sion
µ
PD78078
µ
PD78070A
µ
PD780018
For control
88 pins
61 pins
—
2ch
2ch
2ch
3ch (UART:1ch)
88 pins
69 pins
2.0 V
µ
PD78058F
µ
PD78054
µ
PD78018F
µ
PD78014
µ
PD780001
µ
PD78002
µ
PD78083
µ
PD780208
—
2ch
53 pins
1.8 V
2.7 V
—
—
1ch
—
—
8ch
1ch
8ch
—
1ch
39 pins
53 pins
—
1ch (UART:1ch)
2ch
33 pins
74 pins
68 pins
1.8 V
2.7 V
—
—
32K-60K
16K-40K
32K-48K
24K-32K
48K-60K
32K
16K-32K
32K-60K
2ch
1ch
1ch
For FIP
driving
µ
PD78044F
µ
PD78044H
µ
PD78024
1ch
2ch
2ch
1ch
1ch
1ch
8ch
—
3ch (UART:1ch)
2ch (UART:1ch)
54 pins
57 pins
1.8 V
2.0 V
—
For LCD
driving
Compatible
with IEBus
µ
PD780308
µ
PD78064B
µ
PD78064
µ
PD78098
2ch
1ch
1ch
1ch
8ch
2ch
3ch (UART:1ch)
69 pins
2.7 V
For LV
µ
PD78P0914 32K
6ch
—
—
1ch
8ch
—
2ch
54 pins
4.5 V
3
µ
PD78044H, 78045H, 78046H
FUNCTIONAL OUTLINE
Product name
Item
Internal
memory
ROM
Internal high-speed RAM
FIP display RAM
General registers
Instruction
cycle
µ
PD78044H
32K bytes
1024 bytes
48 bytes
µ
PD78045H
40K bytes
µ
PD78046H
48K bytes
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
Variable instruction execution time
For main system clock
For subsystem clock
0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s/6.4
µ
s (at 5.0 MHz)
122
µ
s (at 32.768 kHz)
• Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
• Bit (set, reset, test, Boolean algebra)
Instruction set
I/O ports (including those
multiplexed with FIP pins)
Total
• CMOS input
• CMOS I/O
• N-ch open-drain
• P-ch open-drain I/O
• P-ch open-drain output
: 68 lines
:
2 lines
: 19 lines
: 13 lines
: 16 lines
: 18 lines
FIP controller/driver
Total
• Segments
• Digits
: 34 lines
: 9 to 24 lines
: 2 to 16 lines
A/D converter
• 8-bit resolution
×
8 channels
• Power supply voltage: AV
DD
= 4.0 to 5.5 V
Serial interface
Timer
• 3-wire serial I/O mode
: 1 channel
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer
• Watchdog timer
: 1 channel
: 1 channel
Timer output
Clock output
3 lines (one for 14-bit PWM output)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(main system clock: when operating at 5.0 MHz)
32.768 kHz (subsystem clock: when operating at 32.768 kHz)
Buzzer output
Vectored
interrupt
Maskable interrupt
Non-maskable interrupt
Software interrupt
Text input
Power supply voltage
Package
1.2 kHz, 2.4 kHz, 4.9 kHz (main system clock: when operating at 5.0 MHz)
Internal 8 lines, external 4 lines
Internal 1 line
1 line
Internal 1 line
V
DD
= 2.7 to 5.5 V
80-pin plastic QFP (14
×
20 mm)
4
µ
PD78044H, 78045H, 78046H
CONTENTS
1.
2.
3.
PIN CONFIGURATION (TOP VIEW) .........................................................................................
BLOCK DIAGRAM ......................................................................................................................
PIN FUNCTIONS .........................................................................................................................
3.1 PORT PINS ..........................................................................................................................................
3.2 PINS OTHER THAN PORT PINS .......................................................................................................
3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ...........................................................
6
8
9
9
11
12
4.
5.
MEMORY SPACE .......................................................................................................................
PERIPHERAL HARDWARE FUNCTIONS ................................................................................
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
PORTS .............................................................................................................................................
CLOCK GENERATOR CIRCUIT ....................................................................................................
TIMER/EVENT COUNTER ..............................................................................................................
CLOCK OUTPUT CONTROL CIRCUIT .........................................................................................
BUZZER OUTPUT CONTROL CIRCUIT .......................................................................................
A/D CONVERTER ...........................................................................................................................
SERIAL INTERFACE ......................................................................................................................
FIP CONTROLLER/DRIVER ..........................................................................................................
15
16
16
17
17
20
20
21
22
23
6.
INTERRUPT FUNCTION AND TEST FUNCTION .....................................................................
6.1
6.2
INTERRUPT FUNCTION .................................................................................................................
TEST FUNCTION ............................................................................................................................
25
25
28
7.
8.
9.
STANDBY FUNCTION ................................................................................................................
RESET FUNCTION .....................................................................................................................
INSTRUCTION SET ....................................................................................................................
29
29
30
33
50
51
52
54
10. ELECTRICAL SPECIFICATIONS ..............................................................................................
11. PACKAGE DRAWING ................................................................................................................
12. RECOMMENDED SOLDERING CONDITIONS .........................................................................
APPENDIX A DEVELOPMENT TOOLS .........................................................................................
APPENDIX B RELATED DOCUMENTS.........................................................................................
5
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