DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
256MB
512MB
1GB
2GB
-
-
-
-
W1D32M72R8
W1D64M72R8
W1D128M72R8
W1D256M72R8 (Preliminary*)
Figure 1: Available layouts
Layout A:
1.181"
Features:
•
•
•
•
•
•
•
•
•
•
•
•
240-pin Registered ECC DDR2 SDRAM Dual-In-
Line Memory Module for DDR2-400 and DDR2-533
JEDEC standard VDD=1.8V (+/- 0.1V) power
supply
One rank 256MB, 512MB, 1GB, and 2GB
Modules are built with 18 x8 DDR2 SDRAM
devices in a 60-ball FBGA package
ECC error detection and correction
Programmable CAS Latency of 3 and 4; Burst
Length of 4 and 8
Auto Refresh and Self Refresh Mode
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
SPD (Serial Presence Detect) with EEPROM
All input/output are SSTL_18 compatible
All contacts are gold plated
One clock delay for register
Layout B:
1.0"
Front view of double-sided DIMM (see detail physical dimensions
at the back)
Speed Grades:
-5
-3.75
Units
Module Speed Grade
PC2-3200 PC2-4200
Speed @ CL3
400
-
MHz
Speed @ CL4
400
533
MHz
Speed @ CL5
-
533
MHz
Note: See Product ordering for full naming guide
Speed Grade
Description:
The following specification covers the W1D32M72R8, W1D64M72R8, W1D128M72R8, and W1D256M72R8
family of Single-Rank Registered ECC DDR2 modules using x8 FBGA SDRAMs. Please reference Figure 1 for
available layout configurations and the product ordering guide on the final page of this specification for available
options including speed grade and silicon manufacturer.
Address Summary Table:
Module Configuration
Refresh
Device Configuration
Row Addressing
Column Addressing
Module Rank
256MB
32M x 72
8k
32M x 8
(9 components)
A0-A13
A0-A9
1
512MB
64M x 72
8K
64M x 8
(9 components)
A0-A13
A0-A9
1
1GB
128M x 72
8K
128M x 8
(9 components)
A0-A14
A0-A9
1
2GB
256M x 72
8K
256M x 8
(9 components)
A0-A14
A0-A9
1
*Specifications are for reference purposes only and are subject to change by Wintec without notice.
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
1
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Pin Configuration:
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
DQ19
61
A4
91
VSS
121
VSS
151
VSS
VSS
62 VDDQ
92 DQS5# 122
DQ4
152
DQ28
DQ24
63
A2
93
DQS5 123
DQ5
153
DQ29
DQ25
64 VDD
94
VSS
124
VSS
154
VSS
VSS
KEY
95
DQ42
125
DM0/DQS9
155
DM3/DQS12
DQS3# 65 VSS
96
DQ43
126
NC/DQS9#
156
NC/DQS12#
DQS3
66 VSS
97
VSS
127
VSS
157
VSS
VSS
67 VDD
98
DQ48
128
DQ6
158
DQ30
DQ26
68
NC
99
DQ49
129
DQ7
159
DQ31
DQ27
69 VDD
100
VSS
130
VSS
160
VSS
VSS
70 A10/AP 101
SA2
131
DQ12
161
CB4
1
CB0
71
BA0
102
NC,TEST
132
DQ13
162
CB5
CB1
72 VDDQ 103
VSS
133
VSS
163
VSS
VSS
73 WE#
104 DQS6# 134
DM1/DQS10
164
DM8/DQS17
DQS8# 74 CAS# 105 DQS6 135
NC/DQS10#
165
NC/DQS17#
DQS8
75 VDDQ 106
VSS
136
VSS
166
VSS
VSS
76
S1#
107
DQ50
137
RFU
167
CB6
CB2
77 ODT1 108
DQ51
138
RFU
168
CB7
CB3
78 VDDQ 109
VSS
139
VSS
169
VSS
VSS
79 VSS
110
DQ56
140
DQ14
170
VDDQ
VDDQ
80 DQ32 111
DQ57
141
DQ15
171
CKE1
CKE0
81 DQ33 112
VSS
142
VSS
172
VDD
VDD
82 VSS
113 DQS7# 143
DQ20
173
A15
A16,BA2 83 DQS4# 114 DQS7 144
DQ21
174
A14
NC
84 DQS4 115
VSS
145
VSS
175
VDDQ
VDDQ
85 VSS
116
DQ58
146
DM2/DQS11
176
A12
A11
86 DQ34 117
DQ59
147
NC/DQS11#
177
A9
A7
87 DQ35 118
VSS
148
VSS
178
VDD
VDD
88 VSS
119
SDA
149
DQ22
179
A8
A5
89 DQ40 120
SCL
150
DQ23
180
A6
90 DQ41
NC - No Connect, RFU - Reserved for Future Use
1.
The Test pin (Pin 102) is reserved for bus analysis and is not connected on normal memory modules
2.
CKE1 and S1# pin are used for dual-rank Registered DIMM
3.
A13 (Pin 196) is for 512MB and above DIMM.
Symbol
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
RESET#
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin
211
212
213
214
215
185
216
186
217
187
218
188
219
189
220
190
221
191
222
192
223
193
224
194
225
195
226
196
227
197
228
198
229
199
230
200
231
201
232
202
DM4/DQS13
233
203
NC/DQS13#
234
204
VSS
235
205
DQ38
236
206
DQ39
237
207
VSS
238
208
DQ44
239
209
DQ45
240
210
VSS
Pin
181
182
183
184
Symbol
VDDQ
A3
A1
VDD
KEY
CK0
CK0#
VDD
A0
VDD
BA1
VDDQ
RAS#
S0#
VDDQ
ODT0
A13
VDD
VSS
DQ36
DQ37
VSS
Symbol
DM5/DQS14
NC/DQS14#
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
RFU
RFU
VSS
DM6/DQS15
NC/DQS15#
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7/DQS16
NC/DQS16#
VSS
DQ62
DQ63
VSS
VDDSPD
SA0
SA1
Pin Locations:
Front View
Pin 1
Pin 240
64
185
65
184
121
120
Back View
240-pin DIMM
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
2
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Functional Block Diagram:
Single Rank 32M x 72 (256MB), 64M x 72 (512MB), 128M x 72 (1GB), and 256M x 72 (2GB) DDR2 Registered
SDRAM DIMM (x8 organization)
RCS0#
DQS0
DQS0#
DM0/DQS9
DQS9#
DQ[0:7]
8
DQS1
DQS1#
DM1/DQS10
NU/
DM/ CS# DQS# DQS
RDQS# RDQS
NU/
DM/ CS# DQS# DQS
RDQS# RDQS
DQS4
DQS4#
DM4/DQS13
DQS13#
DQ[32:39]
8
DQS5
DQS5#
DM5/DQS14
NU/
DM/ CS# DQS# DQS
RDQS# RDQS
NU/
DM/ CS# DQS# DQS
RDQS# RDQS
U0
U4
DQS10#
DQ[8:15]
8
DQS2
DQS2#
DM2/DQS11
DQS14#
DQ[40:47]
8
DQS6
DQS6#
DM6/DQS15
U1
U5
DQS11#
DQ[16:23]
8
DQS3
DQS3#
DM3/DQS12
NU/
DM/ CS# DQS# DQS
RDQS# RDQS
DQS15#
DQ[48:55]
8
DQS7
DQS7#
DM7/DQS16
NU/
DM/ CS# DQS# DQS
RDQS# RDQS
U2
U6
DQS12#
DQ[24:31]
8
DQS8
DQS8#
DM8/DQS17
NU/
DM/ CS# DQS# DQS
RDQS# RDQS
DQS16#
DQ[56:63]
8
NU/
DM/ CS# DQS# DQS
RDQS# RDQS
U3
U7
DQS17#
CB[0:7]
8
NU/
DM/ CS# DQS# DQS
RDQS# RDQS
V
DDSPD
V
DD
/V
DDQ
V
REF
Vss
SERIAL PD
SCL
A0
SA0
A1
SA1
A2
SA2
U8
To SPD
To U0 - U8
To U0 - U8
To U0 - U8
SDA
BA0-BA1
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
CS0#*
RESET#
R
E
G
I
S
T
E
R
RST#
RBA0-RBA1 -> BA0-BA1 to U0 - U8
RA0-RA13 -> A0-A13 to U0 - U8
RRAS# -> RAS# to U0 - U8
RCAS# -> CAS# to U0 - U8
RWE# -> WE# to U0 - U8
RCKE0 -> CKE0 to U0 - U8
RODT0 -> ODT0 to U0 - U8
RS0# -> CS0# to U0 - U8
CK0
CK0#
RESET#
P
L
L
CK to U0 - U8
CK# to U0 - U8
CK to all registers
CK# to all registers
Note:
1. *) CS0# connects to DCS# of Register 1 and CSR# of Register 2;
CSR# of Register 1 and DCS# of Register 2 connects to VDD
2. DQ/DM/DQS, address and control resistor values are 22 Ohms.
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
3
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Absolute Maximum Ratings:
Exposure to stresses greater than these absolute maximum rating conditions for extended periods may affect
reliability of the module.
Symbol
V
DD
V
DD
Q
V
DD
L
V
IN
, V
OUT
T
STG
T
OPR
I
IL
I
OL
Parameter
V
DD
supply voltage relative to V
SS
V
DD
Q supply voltage relative to V
SS
V
DD
L supply voltage relative to V
SS
Voltage on any pin relative to V
SS
Storage temperature (T
case
)
Operating Temperature (Ambient)
Input Leakage Current; Any input 0V
≤
V
IN
≤
0.95V
Output Leakage Current; 0V
≤
V
OUT
≤
V
DD
Q; DQS and ODT are disabled
Min
-1.0
-0.5
-0.5
-0.5
-55
0
-5
-5
Max Units
2.3
2.3
2.3
2.3
+100
+55
5
5
V
V
V
V
°C
°C
µA
µA
DC Operating Conditions:
Parameter
Supply Voltage
V
DD
L Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Symbol
V
DD
V
DD
L
V
DD
Q
V
REF
V
TT
Min
1.7
1.7
1.7
0.49 x V
DD
Q
V
REF
- 40
Nom
1.8
1.8
1.8
0.50 x V
DD
Q
V
REF
Max
1.9
1.9
1.9
0.51 x V
DD
Q
V
REF
+ 40
Units Notes
V
V
V
V
mV
1
4
4
2
3
NOTE:
1. V
DD
and V
DD
Q must keep track of each other. V
DD
Q cannot exceed the value of V
DD
2. V
REF
is expected to equal V
DD
Q/2 of the transmitting device and to track variations in the DC level of the same
3. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to
be set equal to V
REF
and must track variations in the DC level of V
REF
4. V
DD
Q must tracks V
DD
; and V
DD
L tracks V
DD
Input/Output Capacitance:
V
DD
= +1.8V ± 0.1V, V
DD
Q = +1.8V ± 0.1V, V
REF
= V
SS
, f =100MHz, 0°C<T
OPR
<+55°C, V
OUT
(DC) = V
DD
Q/2
Parameter
Input Capacitance:
CK,
CK
Delta Input Capacitance:
CK,
CK
Input Capacitance: BA0, BA1, A0-A12,
CS
,
RAS
,
CAS
,
WE
, CKE, ODT
Delta Input Capacitance: BA0, BA1, A0-A12,
CS
,
RAS
,
CAS
,
WE
, CKE, ODT
Input/Output Capacitance: DQs, DQS, DM, NF
Delta Input/Output Capacitance: DQs, DQS, DM, NF
Symbol
CCK
CDCK
CI
CDI
CIO
CDIO
Min
1.0
-
1.0
-
3.0
-
Max
2.0
0.25
2.0
0.25
4.0
0.5
Units
pF
pF
pF
pF
pF
pF
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
4
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
IDD Specifications and Conditions (256MB - 32Mx8, 9 components):
Symbol
IDD0
Parameter
Operating Current
DRAM IC
Manufacturer*
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
MT
INF
SAM
-5
DDR2-400
675
N/A
1265
765
N/A
1330
32
N/A
495
189
N/A
665
225
N/A
670
135
N/A
720
63
N/A
365
288
N/A
1065
1125
N/A
1635
990
N/A
1520
1485
N/A
1900
27
N/A
485
2070
N/A
2885
-3.75
DDR2-533
720
N/A
1420
810
N/A
1540
45
N/A
535
225
N/A
715
270
N/A
730
171
N/A
750
81
N/A
375
351
N/A
1180
1440
N/A
2115
1260
N/A
1840
1530
N/A
2005
27
N/A
555
2160
N/A
2975
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
Operating Current
IDD2P
Precharge Power-Down Current
IDD2Q
Precharge Quiet Standby Current
IDD2N
Precharge Standby Current
IDD3P
Active Power-Down Standby Current
MRS(12) = 0
Active Power-Down Standby Current
MRS(12) = 1
IDD3N
Active Standby Current
IDD4W
Operating Current Burst Write
IDD4R
Operating Current Burst Read
IDD5B
Burst Auto-Refresh Current
IDD6
Self Refresh Current
IDD7
Operating Current
Note:
DRAM IC Manufacturer* - MT = Micron, INF = Infineon, SAM=Samsung
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
