Advance Information
CAT24FC32
32K-Bit Fast Mode I
2
C Serial CMOS EEPROM
FEATURES
s
Fast mode I
2
C bus compatible*
s
Max clock frequency:
s
Random and sequential read modes
s
Schmitt trigger and spike suppression at SDA
400 kHz for V
CC
=1.8V to 5.5V
1 MHz for V
CC
=2.5V to 5.5V
s
Hardware write protect for entire array
s
Cascadable for up to eight devices
s
32-Byte page or byte write modes
s
Self-timed write cycle with autoclear
s
5 ms max write cycle time
and SCL inputs
s
Output slope control to eliminate ground
bounce
s
Zero standby current
s
Commercial, industrial and automotive
temperature ranges
s
1,000,000 program/erase cycles
s
100 years data retention
s
8-pin PDIP, 8-pin SOIC (150 and 200 mil) and
8-pin TSSOP packages
DESCRIPTION
The CAT24FC32 is a 32K-bit Serial CMOS EEPROM
internally organized as 4Kx8 bits. The device is
compatible with Fast-mode I
2
C bus specification and
operates down to 1.8V with a bit rate up to 400 kbit/s and
1MHz for V
CC
≥
2.5V. Extended addressing capability
allows up to 8 devices to share the same bus. Catalyst's
advanced CMOS technology substantially reduces
device power requirements. The device is optimized for
high performance applications, where low power, low
voltage and high speed operation are required.
CAT24FC32 is available in 8-pin DIP, 8-pin SOIC (JEDEC
and EIAJ) and 8-pin TSSOP packages.
PIN CONFIGURATION
DIP Package (P)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
VSS
BLOCK DIAGRAM
TSSOP Package (U)
1
2
3
4
8
7
6
5
EXTERNAL LOAD
DOUT
SENSE AMPS
SHIFT REGISTERS
VCC
WP
SCL
SDA
VCC
VSS
ACK
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
256
SDA
START/STOP
LOGIC
SOIC Package (J,K)
XDEC
128
EEPROM
128 X 256
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
WP
CONTROL
LOGIC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1020, Rev. F
CAT24FC32
Advance Information
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
Power Supply
Ground
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
1,000,000
100
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
RECOMMENDED OPERATING CONDITIONS
Temperature Range
Commercial
Industrial
Automotive
Extended
Minimum
0˚C
-40˚C
-40˚C
-40˚C
Maximum
+70˚C
+85˚C
+105˚C
+125˚C
Supply Voltage Range
2.5V to 5.5V
1.8V to 5.5V
Device
CAT24FC32
CAT24FC32-1.8
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
Doc. No. 1020, Rev. F
2
Advance Information
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions, unless otherwise specified
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB(1)
V
IL(2)
V
IH(2)
V
OL1
V
OL2
Parameter
Input Leakage Current
(4)
Output Leakage Current
(4)
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Standby Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
-0.5
0.7V
CC
0
0.3V
CC
V
CC
+ 0.5
0.4
0.2V
CC
µA
V
V
V
V
400
µA
Min.
-10
-10
Typ.
Max.
10
10
3
Units
µA
µA
mA
CAT24FC32
Test Conditions
V
IN
= GND to V
CC
V
IN
= GND to V
CC
f
SCL
= 400kHz
V
CC
= 5.5V
f
SCL
= 400kHz
V
CC
= 5.5V
V
CC
= 5.5V
V
IN
= GND or V
CC
2.5V
≤
V
CC
≤
5.5V
I
OL
= 3.0 mA
1.8V
≤
V
CC
< 2.5V
I
OL
= 3 mA
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Max.
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Note:
(1) Standby current, I
SB
< 900 nA; A0, A1, A2, WP connected to GND; SCL, SDA = GND or VCC.
(2) V
IL
min and V
IH
max are reference values only and are not tested.
(3) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(4) I/O pins, SDA and SCL do not obstruct the bus lines if V
CC
is switched off.
3
Doc. No. 1020, Rev. F
CAT24FC32
Advance Information
A.C. CHARACTERISTICS
Over recommended operating conditions, unless otherwise specified (Note 1).
Read & Write Cycle Limits
Symbol
Parameter
V
CC
= 1.8V - 5.5V
Min.
f
SCL
t
SP
t
LOW
t
HIGH
t
R(2)
t
F(2)
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
SU:WP
t
HD:WP
t
AA
t
DH
t
BUF(2)
t
OF(2)
t
WC(3)
Clock Frequency
Input Filter Spike
Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time
(for a Repeated Start)
Data Input Hold Time
Data In Setup Time
Stop Condition Setup Time
WP Setup Time
WP Hold Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before
a New Transmission Can Start
Output Fall Time from V
IH
min to
V
IL
max
Write Cycle Time (Byte or Page)
5
5
ms
20
250
20
100
ns
50
1.3
1.3
0.6
20
20
0.6
0.6
0
100
0.6
0
2.5
900
50
0.5
300
300
Max.
400
50
0.6
0.4
20
20
0.25
0.25
0
50
0.25
0
1
550
300
100
V
CC
= 2.5V - 5.5V
Min.
Max.
1,000
50
kHz
ns
µs
µs
ns
ns
µs
µs
ns
ns
µs
µs
µs
ns
ns
µs
Units
Power-Up Timing
(2)(4)
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Max.
1
1
Units
ms
ms
Note:
(1) Test Conditions according to "AC Test Conditions" Table.
(2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
(4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 1020, Rev. F
4
Advance Information
AC TEST CONDITIONS
Input pulse voltages
Input rise and fall times
Input reference voltages
Output reference voltages
Output load
0.2V
CC
to 0.8V
CC
≤
50 ns
0.3V
CC
, 0.7V
CC
0.5V
CC
Current source: I
OL
= 3mA;
CAT24FC32
CL: 400pF for f
SCl
max = 400kHz / 100pF for f
SCL
max = 1 MHz
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
SDA IN
tAA
SDA OUT
tDH
tBUF
Figure 2. WP Timing
2nd Byte Address
1
SCL
A7
A0
tSU:WP
Data
9
1
8
8
SDA
D7
D0
WP
tHD:WP
Figure 3. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5
Doc. No. 1020, Rev. F
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
