PRELIMINARY PRODUCT INFORMATION
µ
PD780016Y, 780018Y
8-BIT SINGLE-CHIP MICROCONTROLLER
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD780016Y and 780018Y are members of the
µ
PD780018Y subseries of the 78K/0 series microcontrollers.
Besides a high-speed, high-performance CPU, these microcontrollers have on-chip ROM, RAM, I/O ports, timer,
serial interface, real-time output port, interrupt control, and various other peripheral hardware.
The
µ
PD78P0018Y devices including a one-time PROM version and an EPROM version, both of which can operate
in the same power supply voltage range as a mask ROM version, and various development tools are available.
The details of the functions are described in the following user’s manuals. Be sure to read it before starting design.
µ
PD780018,780018Y Subseries User’s Manual: U11754E
78K/0 Series User’s Manual – Instructions
: IEU-1372
FEATURES
•
Internal high capacity ROM and RAM
Item
Part
Number
Program
Memory
(ROM)
48K bytes
60K bytes
Data Memory
Internal High-Speed
RAM
1024 bytes
Buffer RAM
Internal Extended
RAM
1024 bytes
(14
×
20 mm)
Package
µ
PD780016Y
µ
PD780018Y
32 bytes
100-pin plastic QFP
• External memory expansion space: 64K bytes
•
Instruction execution time can be changed from
high-speed (0.4
µ
s) to ultra-low-speed (122
µ
s)
•
I/O ports: 88
•
Serial interface: 3 channels
• 3-wire serial I/O mode
(with automatic data transmit/receive function): 1 channel
• 3-wire serial I/O mode
(with time division transfer function): 1 channel
• I
2
C bus mode (supporting multi-task): 1 channel
•
Supply voltage : V
DD
= 2.7 to 5.5 V
•
8-bit resolution A/D converter: 8 channels
•
Timer: 7 channels
APPLICATION FIELD
Cellular phones, cordless phones, AV equipment, etc.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Document No. U11810EJ1V0PM00 (1st edition)
Date Published December 1996 N
Printed in Japan
©
1996
µ
PD780016Y, 780018Y
ORDERING INFORMATION
Part Number
Package
100-pin plastic QFP (14
×
20 mm)
100-pin plastic QFP (14
×
20 mm)
µ
PD780016YGF-XXX-3BA
µ
PD780018YGF-XXX-3BA
Remark
XXX indicates ROM code suffix.
78K/0 SERIES DEVELOPMENT
These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are
subseries names.
Under mass production
Under development
Y subseries supports I
2
C bus.
For control
100-pin
100-pin
100-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
42/44-pin
µ
PD78078
µ
PD78070A
µ
PD780018
µ
PD78054
µ
PD780034
µ
PD780024
µ
PD780964
µ
PD780924
µ
PD78014H
µ
PD78018F
µ
PD78014
µ
PD780001
µ
PD78002
µ
PD78083
For driving FIP
TM
Note
µ
PD78078Y
µ
PD78070AY
µ
PD780018Y
µ
PD78054Y
µ
PD780034Y
µ
PD780024Y
Note
Timer added to the
µ
PD78054, external interface functions enhanced
ROM-less product for the
µ
PD78078
Enhanced serial I/O of the
µ
PD78078, functions limited
Reduced EMI noise product of the
µ
PD78054
UART and D/A added to the
µ
PD78014, enhanced I/O
Enhanced A/D of the
µ
PD780024
Enhanced serial I/O of the
µ
PD78018F. Reduced EMI noise product.
Enhanced A/D of the
µ
PD780924
Internal inverter control circuit and UART. Reduced EMI noise product.
Reduced EMI noise of the
µ
PD78018F.
Low-voltage (1.8 V) operation product of the
µ
PD78014, ROM, RAM variations enhanced
A/D, 16-bit timer added to the
µ
PD78002
A/D added to the
µ
PD78002
Basic subseries for control
Internal UART, low-voltage (1.8 V) operation possible
µ
PD78058F
µ
PD78058FY
µ
PD78018FY
µ
PD78014Y
µ
PD78002Y
78K/0
series
100-pin
80-pin
64-pin
µ
PD780208
µ
PD78044F
µ
PD78024
I/O, FIP C/D of the
µ
PD78044F enhanced, display output total: 53
6-bit U/D counter added to the
µ
PD78024, display output total: 34
Basic subseries for FIP driving, display output total: 26
For driving LCD
100-pin
100-pin
100-pin
µ
PD780308
µ
PD78064B
µ
PD78064
Supporting IEBus
TM
µ
PD780308Y
µ
PD78064Y
Enhanced SIO of the
µ
PD78064, ROM, RAM extended
Reduced EMI noise product of the
µ
PD78064
Basic subseries for LCD driving, internal UART
80-pin
µ
PD78098
For LV
IEBus controller added to the
µ
PD78054
64-pin
µ
PD78P0914
PWM output, internal LV digital code decoder, Hsync counter
Note
Under planning
2
µ
PD780016Y, 780018Y
The major functional differences among the subseries are shown below.
Function
Subseries Name
For Control
µ
PD78078
ROM
Capacity
Timer
8-bit 16-bit Watch WDT
1ch
1ch
1ch
8-bit 10-bit 8-bit
A/D A/D D/A
8ch
—
2ch
Serial
Interface
3ch (UART: 1ch)
V
DD
External
MIN.
Eexpansion
Value
1.8 V
2.7 V
I/O
32 K-60 K 4ch
—
88
61
µ
PD78070A
µ
PD78058F
µ
PD78054
µ
PD780024
µ
PD780964
µ
PD780924
µ
PD78014H
µ
PD780018 48 K-60 K
2ch
16 K-60 K
—
8ch
3ch
Note
—
—
8ch
2ch
1ch
1ch
8ch
—
8ch
—
—
2ch
2ch
3ch (UART: 1ch)
88
69
2.0 V
µ
PD780034 8 K-32 K
—
51
1.8 V
2ch (UART: 2ch)
47
2.7 V
2ch
53
1.8 V
µ
PD78018F 8 K-60 K
µ
PD78014
µ
PD78002
µ
PD78083
For FIP
driving
8 K-32 K
—
—
1ch
—
1ch
1ch
1ch
—
8ch
8ch
—
—
1ch (UART: 1ch)
2ch
1ch
39
53
33
74
68
54
1ch
1ch
1ch
8ch
—
—
3ch (UART: 1ch)
2ch (UART: 1ch)
57
1.8 V
2.0 V
—
1.8 V
2.7 V
—
—
2.7 V
—
µ
PD780001 8 K
8 K-16 K
µ
PD780208 32 K-60 K 2ch
µ
PD78044F 16 K-40 K
µ
PD78024
24 K-32 K
For LCD
driving
µ
PD780308 48 K-60 K 2ch
µ
PD78064B 32 K
µ
PD78064
16 K-32 K
32 K-60 K 2ch
6ch
For IEBus
For LV
µ
PD78098
1ch
—
1ch
—
1ch
1ch
8ch
8ch
—
—
2ch
—
3ch (UART: 1ch)
2ch
69
54
2.7 V
4.5 V
µ
PD78P0914 32 K
Note
10-bit timer: 1 channel
3
µ
PD780016Y, 780018Y
OVERVIEW OF FUNCTION
Part Number
Item
Internal
memory
ROM
Internal high-speed RAM
Buffer RAM
Internal expansion RAM
Memory space
General registers
Instruction cycle
When main system clock selected
When subsystem clock selected
Instruction set
48K bytes
1024 bytes
32 butes
1024 bytes
64K bytes
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
On-chip instruction execution time selective function
0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s/6.4
µ
s (at 5.0 MHz)
122
µ
s (at 32.768 kHz)
•
•
•
•
16-bit operation
Multiplcation/division (8 bits
×
8 bits,16 bits
÷
8 bits)
Bit manipulation (set, reset, test, boolean operation)
BCD adjustment, etc.
Total
• CMOS input
• CMOS I/O
A/D converter
Serial interface
: 88
:
9
60K bytes
µ
PD780016Y
µ
PD780018Y
I/O ports
: 79
• 8-bit resolution
×
8 channels
• 3-wire serial I/O mode (with automatic data transmit/receive function): 1 channel
• 3-wire serial I/O mode (with time division transfer function)
: 1 channel
2
• I C bus mode (supporting multi-task)
: 1 channel
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 4 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
5 (14-bit PWM output
×
1, 8-bit PWM output
×
2)
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz
(at main system clock of 5.0 MHz)
32.768 kHz (at subsystem clock of 32.768 kHz)
Timer
Timer output
Clock output
Buzzer output
Vectored
interrupt
sources
Maskable
2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: at 5.0 MHz)
Internal : 12
External : 7
Internal : 1
1
Internal : 1
External : 1
V
DD
= 2.7 to 5.5 V
• 100-pin plastic QFP (14
×
20 mm)
Non-maskable
Software
Test input
Supply voltage
Package
4
µ
PD780016Y, 780018Y
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 6
2. BLOCK DIAGRAM .............................................................................................................................. 8
3. PIN FUNCTIONS ................................................................................................................................. 9
3.1
3.2
3.3
Port Pins ...................................................................................................................................................... 9
Non-port Pins ............................................................................................................................................ 11
Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 13
4. MEMORY SPACE .............................................................................................................................. 16
5. PERIPHERAL HARDWARE FUNCTIONS ....................................................................................... 17
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Ports ........................................................................................................................................................... 17
Clock Generator ........................................................................................................................................ 18
Timer/Event Counter ................................................................................................................................ 18
Clock Output Control Circuit .................................................................................................................. 22
Buzzer Output Control Circuit ................................................................................................................ 22
A/D Converter ........................................................................................................................................... 23
Serial Interfaces ........................................................................................................................................ 24
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS ....................................................................... 26
6.1
6.2
Interrupt Functions .................................................................................................................................. 26
Test Functions .......................................................................................................................................... 29
7. EXTERNAL DEVICE EXPANSION FUNCTIONS ............................................................................. 30
8. STANDBY FUNCTION ...................................................................................................................... 30
9. RESET FUNCTION ............................................................................................................................ 31
10. INSTRUCTION SET ........................................................................................................................... 32
11. PACKAGE DRAWINGS ..................................................................................................................... 34
APPENDIX A. DEVELOPMENT TOOLS................................................................................................ 35
APPENDIX B. RELATED DOCUMENTS ............................................................................................... 37
5
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