MicreL, Inc.
Precision Edge
3.3V 1GHz DUAL 1:10 PRECISION
SY89828L
Precision Edge
®
LVDS FANOUT BUFFER/
SY89828L
TRANSLATOR WITH 2:1 INPUT MUX
®
FEATURES
■
High-performance dual 1:10, 1GHz LVDS fanout
buffer/translator
■
Two banks of 10 differential LVDS outputs
■
Guaranteed AC parameters over temperature and
voltage:
• > 1GHz f
MAX
• < 50ps within device skew
• < 400ps t
r
, t
f
time
■
Each bank includes a 2:1 input mux
■
2:1 mux input accepts LVDS and LVPECL
■
Low jitter performance
• < 1ps
RMS
cycle-to-cycle jitter
• < 1ps
PP
total jitter
■
3.3V supply voltage
■
Output enable function
■
LVDS input includes internal 100
Ω
termination
■
Available in a 64-Pin EPAD-TQFP
Precision Edge
®
DESCRIPTION
The SY89828L is a precision fanout buffer with 20
differential LVDS (Low Voltage Differential Swing) output
pairs. The part is designed for use in low voltage 3.3V
applications that require a large number of outputs to drive
precisely aligned, ultra low-skew signals to their destination.
The input is multiplexed from either LVDS or LVPECL (Low
Voltage Positive Emitter Coupled Logic) by the CLK_SEL1
and CLK_SEL2 pins. The Output Enables (OE1 and OE2)
are synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
The SY89828L features a low pin-to-pin skew of less
than 50ps—performance previously unachievable in a
standard product having such a high number of outputs.
The SY89828L is available in a single space saving package,
enabling a lower overall cost solution.
APPLICATIONS
■
Enterprise networking
■
High-end servers
■
Communications
TYPICAL APPLICATION CIRCUIT
100Ω
Primary
Card
Primary Clock Source
LVDS_CLKA
/LVDS_CLKA
5
5
Backup Clock Source
LVDS_CLKB
/LVDS_CLKB
5
5
100Ω
Redundant
Card
SEL1
Primary/Backup Clock Select
(Switchover with 2.0ns)
System using SY89828L as a switchover circuit from a Primary Clock to a Redundant backup Clock in a fail-safe application.
LVPECL inputs not shown in this application.
Precision Edge is a registered trademark of Micrel, Inc.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: January 2008
Micrel, Inc.
Precision Edge
®
SY89828L
PACKAGE/ORDERING INFORMATION
VCCO
Q0
/Q0
Q1
/Q1
Q2
/Q2
Q3
/Q3
Q4
/Q4
Q5
/Q5
Q6
/Q6
VCCO
Ordering Information
(1)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GNDO
Q7
/Q7
Q8
/Q8
Q9
/Q9
VCCO
VCCO
Q10
/Q10
Q11
/Q11
Q12
/Q12
GNDO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SEL2
LVDS_CLKB
/LVDS_CLKB
VCCI
LVDS_CLKA
/LVDS_CLKA
CLK_SEL1
LVPECL_CLKA
/LVPECL_CLKA
GNDI
OE1
LVPECL_CLKB
/LVPECL_CLKB
CLK_SEL2
OE2
SEL1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCCO
/Q19
Q19
/Q18
Q18
/Q17
Q17
/Q16
Q16
/Q15
Q15
/Q14
Q14
/Q13
Q13
VCCO
Part Number
SY89828LHI
(2)
SY89828LHITR
(2)
SY89828LHY
(2)
SY89828LHYTR
(2)
Package
Type
H64-1
H64-1
H64-1
H64-1
Operating
Range
Industrial
Industrial
Industrial
Industrial
Package
Marking
SY89828LHI
SY89828LHI
Lead
Finish
Sn-Pb
Sn-Pb
SY89828LHY with
Pb-Free
Pb-Free bar-line indicator Matte-Sn
SY89828LHY with
Pb-Free
Pb-Free bar-line indicator Matte-Sn
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
2. Pb-Free package recommended for new designs.
64-Pin TQFP (H64-1)
FUNCTIONAL BLOCK DIAGRAM
100Ω termination
internal
CLK_SEL1
LVDS_CLKA
/LVDS_CLKA
SEL1
OE1
0
0
10
10
LVPECL_CLKA
/LVPECL_CLKA
Q0 – Q9
/Q0 – /Q9
1
1
100Ω termination
internal
LEN
Q
D
LVDS_CLKB
/LVDS_CLKB
0
0
10
10
Q10 – Q19
/Q10 – /Q19
1
LVPECL_CLKB
/LVPECL_CLKB
D
CLK_SEL2
SEL2
OE2
1
LEN
Q
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
2
MicreL, Inc.
Precision Edge
®
SY89828L
PIN DESCRIPTIONS
Pin Number
5, 6
Pin Name
LVDS_CLKA
/LVDS_CLKA
I/O
Input
Type
LVDS
Internal
P/U
3.5kΩ
Pull-up
See Fig. 2
3.5kΩ
Pull-up
See Fig. 2
75kΩ
pull-down
See Fig. 1
75kΩ
pull-down
See Fig. 1
11kΩ
Pull-up
11kΩ
Pull-up
11kΩ
Pull-up
11kΩ
Pull-up
11kΩ
Pull-up
11kΩ
Pull-up
Pin Function
Differential clock input selected by CLK_SEL1, SEL1 and
SEL2. Can be left floating if not selected. Floating input, if
selected produces an indeterminate output. Has internal
100Ω termination.
Differential clock input selected by CLK_SEL1, SEL1 and
SEL2. Can be left floating if not selected. Floating input, if
selected produces an indeterminate output. Has internal
100Ω termination.
Differential clock input selected by CLK_SEL1, SEL1
and SEL2. Can be left floating. Floating input, if selected
produces a LOW at output. Requires external termination.
Differential clock input selected by CLK_SEL2, SEL1
and SEL2. Requires external termination.
Selects LVDS_CLKA input when LOW and
LVPECL_CLKA input when HIGH.
Selects LVDS_CLKB input when LOW and
LVPECL_CLKB input when HIGH.
Selects input source CLKA when LOW and CLKB
when HIGH for outputs Q0 – Q9 and /Q0 – /Q9.
Selects input source CLKA when LOW and CLKB
when HIGH for outputs Q10 – Q19 and /Q10 – /Q19.
Enable input synchronized internally to prevent output
glitches or runt pulses.
Enable input synchronized internally to prevent output
glitches or runt pulses.
Core VCC connected to 3.3V supply. Not connected to
VCCO internally. Connected to VCCO on PCB.
Bypass with 0.1µF in parallel with 0.01µF low ESR
capacitors as close to VCC pins as possible.
Output buffer VCC connected to 3.3V suppy. Not connected
to VCCI internally. Connected to VCCI on PCB.
Bypass with 0.1µF in parallel with 0.01µF low ESR
capacitors as close to VCC pins as possible.
Core ground not connected to GNDO internally.
To be connected to GNDO on PCB.
Output buffer ground not connected to GNDI internally.
To be connected to GNDI on PCB.
LVDS
Differential clock outputs from CLKA when SEL1 = LOW
and from CLKB when SEL1 = HIGH. Q outputs are static
when OE1 = LOW. Unused output pair must be terminated
with 100Ω to maintain low jitter and skew.
Differential clock outputs (complement) from CLKA when
SEL1 = LOW and from CLKB when SEL1 = HIGH. /Q
outputs are static HIGH when OE1 = LOW. Unused output
pairs must be externally terminated with 100Ω to maintain
low jitter and skew.
Differential outputs from CLKA when SEL2 = LOW and
from CLKB when SEL2 = HIGH. Q outputs are static LOW
when OE2 = LOW. Unused output pairs must be externally
terminated with 100Ω to maintain low jitter and skew.
2, 3
LVDS_CLKB
/LVDS_CLKB
Input
LVDS
8, 9
LVPECL_CLKA
/LVPECL_CLKA
LVPECL_CLKB
/LVPECL_CLKB
CLK_SEL1
CLK_SEL2
SEL1
SEL2
OE1
OE2
VCCI
Input
LVPECL
12, 13
Input
LVPECL
7
14
16
1
11
15
4
Input
Input
Input
Input
Input
Input
Power
LVTTL/
CMOS
LVTTL/
CMOS
LVTTL/
CMOS
LVTTL/
CMOS
LVTTL/
CMOS
LVTTL/
CMOS
17, 32, 40,
41, 49, 64
VCCO
Power
10
33, 48
63, 61, 59, 57, 55
53, 51, 47, 45, 43
GNDI
GNDO
Q0 – Q9
Power
Power
Output
62, 60, 58, 56, 54
52, 50, 46, 44, 42
/Q0 – /Q9
Output
LVDS
39, 37, 35, 31, 29
27, 25, 23, 21, 19
Q10 – Q19
Output
LVDS
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY89828L
Pin Number
38, 36, 34, 30, 28
26, 24, 22, 20, 18
Pin Name
/Q10 – /Q19
I/O
Output
Type
LVDS
Internal
P/U
Pin Function
Differential outputs (complement) from CLKA when SEL2
= LOW and from CLKB when SEL2 = HIGH. /Q outputs
are static HIGH when OE2 = LOW. Unused output
pairs must be externally terminated with 100Ω to maintain
low jitter and skew.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
4
MicreL, Inc.
Precision Edge
®
SY89828L
TRUTH TABLE
OE1
(1)
OE2
(1)
SEL1
(1)
SEL2
(1)
CLK_SEL1
(1)
CLK_SEL2
(1)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
X
X
X
X
0
0
1
1
X
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
X
X
X
X
X
0
1
0
0
1
1
0
0
1
1
X
X
0
1
X
X
0
1
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
X
X
0
1
X
X
0
1
X
Q0 – Q9
/Q0 – /Q9
Q10 – Q19
/Q10 – /Q19
LVDS_CLKA
/LVDS_CLKA
LVDS_CLKA
/LVDS_CLKA
LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA
LVDS_CLKA
/LVDS_CLKA
LVDS_CLKB
/LVDS_CLKB
LVDS_CLKA
/LVDS_CLKA
LVPECL_CLKB /LVPECL_CLKB
LVPECL_CLKA /LVPECL_CLKA
LVDS_CLKB
/LVDS_CLKB
LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB
LVDS_CLKB
/LVDS_CLKB
LVDS_CLKA
/LVDS_CLKA
LVPECL_CLKB /LVPECL_CLKB
LVDS_CLKA
/LVDS_CLKA
LVDS_CLKB
/LVDS_CLKB
LVPECL_CLKA /LVPECL_CLKA
LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA
LVDS_CLKB
/LVDS_CLKB
LVDS_CLKB
/LVDS_CLKB
LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LVDS_CLKA
/LVDS_CLKA
LVPECL_CLKA /LVPECL_CLKA
LVDS_CLKB
/LVDS_CLKB
LVPECL_CLKB /LVPECL_CLKB
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
LVDS_CLKA
/LVDS_CLKA
LVPECL_CLKA /LVPECL_CLKA
LVDS_CLKB
/LVDS_CLKB
LVPECL_CLKB /LVPECL_CLKB
LOW
HIGH
NOTE:
1. Input has internal pull-up so floating input = 1.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
5
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