DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD784035Y,784036Y,784037Y,784038Y
16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The
µ
PD784038Y is based on the
µ
PD784038 with an I
2
C bus control function added, and is ideal for audio-visual
applications.
One-time PROM and EPROM versions, such as the
µ
PD78P4038Y, that can operate in the same voltage range
as mask ROM versions, and various development tools are provided.
The functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing
your system.
µ
PD784038, 784038Y Subseries User’s Manual - Hardware: U11316E
78K/IV Series User’s Manual - Instruction:
U10905E
FEATURES
78K/IV Series
Pin-compatible with
µ
PD78234 Subseries,
Timer/counter 16-bit timer/counter
×
3 units 16-bit
timer
×
1 unit
PWM output: 2 outputs
Standby function
HALT/STOP/IDLE mode
Clock division function
Watchdog timer: 1 channel
Clock output function
Selectable from f
CLK
, f
CLK
/2, f
CLK
/4, f
CLK
/8, and
f
CLK
/16
A/D converter: 8-bit resolution
×
8 channels
D/A converter: 8-bit resolution
×
2 channels
Supply voltage: V
DD
= 2.7 to 5.5 V
2
µ
PD784026 Subseries, and
µ
PD784038
Subseries
Higher internal memory capacity than
µ
PD78234
Subseries and
µ
PD784026 Subseries
Minimum instruction execution time: 125 ns
(@ 32-MHz operation)
I/O ports: 64
Serial interface: 3 channels
UART/IOE (3-wire serial I/O): 2 channels
CSI (3-wire serial I/O, 2-wire serial I/O, I C bus):
1 channel
APPLICATION FIELDS
Cellular phones, cordless phones, audio-visual systems, etc.
Unless contextually excluded, references in this document to the
µ
PD784038Y mean
µ
PD784035Y,
µ
PD784036Y,
and
µ
PD784037Y.
The information in this document is subject to change without notice.
Document No. U10741EJ1V0DS00 (1st edition)
Date Published July 1997 N
Printed in Japan
The mark
5
shows major revised points.
©
1996
µ
PD784035Y, 784036Y, 784037Y, 784038Y
ORDERING INFORMATION
Part Number
Package
Internal ROM (Bytes) Internal RAM (Bytes)
µ
PD784035YGC-×××-3B9
µ
PD784035YGC-×××-8BT
µ
PD784036YGC-×××-3B9
µ
PD784036YGC-×××-8BT
µ
PD784037YGC-×××-3B9
µ
PD784037YGC-×××-8BT
µ
PD784037YGK-×××-BE9
µ
PD784038YGC-×××-3B9
µ
PD784038YGC-×××-8BT
µ
PD784038YGK-×××-BE9
Note
Under development
80-pin plastic QFP (14
×
14 mm, 2.7-mm thick)
80-pin plastic QFP (14
×
14 mm, 1.4-mm thick)
80-pin plastic QFP (14
×
14 mm, 2.7-mm thick)
80-pin plastic QFP (14
×
14 mm, 1.4-mm thick)
80-pin plastic QFP (14
×
14 mm, 2.7-mm thick)
80-pin plastic QFP (14
×
14 mm, 1.4-mm thick)
80-pin plastic TQFP (fine pitch) (12
×
12 mm)
80-pin plastic QFP (14
×
14 mm, 2.7-mm thick)
80-pin plastic QFP (14
×
14 mm, 1.4-mm thick)
80-pin plastic TQFP (fine pitch) (12
×
12 mm)
48 K
48 K
48 K
64 K
64 K
64 K
96 K
96 K
96 K
128 K
128 K
128 K
2048
2048
2048
2048
2048
2048
3584
3584
3584
4352
4352
4352
µ
PD784035YGK-×××-BE9
Note
80-pin plastic TQFP (fine pitch) (12
×
12 mm)
µ
PD784036YGK-×××-BE9
Note
80-pin plastic TQFP (fine pitch) (12
×
12 mm)
Remark
×××
indicates the ROM code suffix.
2
µ
PD784035Y, 784036Y, 784037Y, 784038Y
78K/IV Series Product Development
: Under mass production
: Under development
I
2
C bus supported
Multi-master I
2
C bus supported
µ
PD784038Y
µ
PD784038
µ
PD784225Y
µ
PD784225
80-pin, ROM collection added
Multi-master I
2
C bus supported
Standard models
µ
PD784026
A/D, 16-bit timer,
enhanced power
management
Enhanced internal memory capacity
Pin-compatible with the
µ
PD784026
Multi-master I
2
C bus supported
µ
PD784216Y
µ
PD784216
100-pin, enhanced I/O and
internal memory capacity
µ
PD784218Y
µ
PD784218
Enhanced internal memory
capacity, ROM collection added
µ
PD784054
µ
PD784046
ASSP models
µ
PD784908
On-chip IEBus
TM
controller
On-chip 10-bit A/D
µ
PD78F4943
56-Kbyte flash memory
for CD-ROM
Multi-master I
2
C bus supported
µ
PD784928Y
µ
PD784928
Enhanced functions
of the
µ
PD784915
µ
PD784915
Software servo control
On-chip analog circuit for VCRs
Enhanced timer
3
µ
PD784035Y, 784036Y, 784037Y, 784038Y
FUNCTIONS
Part Number
Item
Number of basic instructions
(mnemonics)
General-purpose register
Minimum instruction execution
time
Internal memory
Memory space
I/O port
Total
Input
I/O
Pins with
ancillary
function
Note
Pins with pull-
up resistor
LEDs direct
drive output
Transistor
direct drive
Real-time output port
Timer/counter
ROM
RAM
113
8 bits
×
16 registers
×
8 banks, or 16 bits
×
8 registers
×
8 banks (memory mapping)
125 ns/250 ns/500 ns/1000 ns (@ 32-MHz operation)
48 KBytes
2048 Bytes
64
8
56
54
24
8
4 bits
×
2 or 8 bits
×
1
Timer/counter 0: Timer register
×
1
(16 bits)
Capture register
×
1
Compare register
×
2
Timer/counter 1: Timer register
×
1
(8/16 bits)
Capture register
×
1
Capture/compare register
×
1
Compare register
×
1
Timer/counter 2: Timer register
×
1
(8/16 bits)
Capture register
×
1
Capture/compare register
×
1
Compare register
×
1
Timer 3:
(8/16 bits)
PWM output
Serial interface
A/D converter
D/A converter
Clock output
Watchdog timer
Standby
Interrupt
Software source
Maskable
Timer register
×
1
Compare register
×
1
Pulse output
• Toggle output
• PWM/PPG output
• One-shot pulse output
Pulse output
• Real-time output (4 bits
×
2)
64 KBytes
96 KBytes
3584 Bytes
128 KBytes
4352 Bytes
µ
PD784035Y
µ
PD784036Y
µ
PD784037Y
µ
PD784038Y
1 MByte with program and data spaces combined
Pulse output
• Toggle output
• PWM/PPG output
12-bit resolution
×
2 channels
UART/IOE (3-wire serial I/O)
: 2 channels (on-chip baud rate generator)
2
C bus) : 1 channel
CSI (3-wire serial I/O, 2-wire serial I/O, I
8-bit resolution
×
8 channels
8-bit resolution
×
2 channels
Selectable from f
CLK
, f
CLK
/2, f
CLK
/4, f
CLK
/8, f
CLK
/16 (can also be used as 1-bit output port)
1 channel
HALT/STOP/IDLE mode
Hardware source 24 (internal: 17, external: 7 (variable sampling clock input: 1))
BRK instruction, BRKCS instruction, operand error
Internal: 16, external: 6
• 4 programmable priority levels
• 3 processing styles: vectored interrupt/macro service/context switching
Non-maskable Internal: 1, external: 1
Supply voltage
Package
V
DD
= 2.7 to 5.5 V
80-pin plastic QFP (14
×
14 mm, 2.7-mm thick)
80-pin plastic QFP (14
×
14 mm, 1.4-mm thick)
80-pin plastic TQFP (fine pitch) (12
×
12 mm)
Note
The pins with ancillary function are included in the I/O pins.
4
µ
PD784035Y, 784036Y, 784037Y, 784038Y
CONTENTS
1.
2.
3.
4.
5.
DIFFERENCES AMONG MODELS IN
µ
PD784038Y SUBSERIES ............................................. 7
MAJOR DIFFERENCES FROM
µ
PD784026 SUBSERIES AND
µ
PD78234 SUBSERIES ........ 8
PIN CONFIGURATION (TOP VIEW) ............................................................................................. 9
BLOCK DIAGRAM ......................................................................................................................... 11
PIN FUNCTION ............................................................................................................................... 12
5.1
5.2
5.3
Port Pins ................................................................................................................................................ 12
Non-Port Pins ....................................................................................................................................... 14
Types of Pin I/O Circuits and Connections for Unused Pins ........................................................ 16
6.
CPU ARCHITECTURE ................................................................................................................... 19
6.1
6.2
Memory Space ...................................................................................................................................... 19
CPU Registers ...................................................................................................................................... 24
6.2.1
6.2.2
6.2.3
General-purpose registers ........................................................................................................ 24
Control registers ........................................................................................................................ 25
Special function registers (SFRs) ............................................................................................. 26
7. PERIPHERAL HARDWARE FUNCTIONS ...................................................................................... 31
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Ports ....................................................................................................................................................... 31
Clock Generation Circuit ..................................................................................................................... 32
Real-Time Output Port ......................................................................................................................... 34
Timer/Counter ....................................................................................................................................... 35
PWM Output (PWM0, PWM1) .............................................................................................................. 37
A/D Converter ....................................................................................................................................... 38
D/A Converter ....................................................................................................................................... 39
Serial Interface ..................................................................................................................................... 40
7.8.1
7.8.2
7.9
Asynchronous serial interface/3-wire serial I/O (UART/IOE) .................................................. 41
Clocked serial interface (CSI) .................................................................................................... 43
Clock Output Function ........................................................................................................................ 44
7.10 Edge Detection Function .................................................................................................................... 45
7.11 Watchdog Timer ................................................................................................................................... 45
8.
INTERRUPT FUNCTION ................................................................................................................ 46
8.1
8.2
8.3
8.4
8.5
Interrupt Sources ................................................................................................................................. 46
Vectored Interrupt ................................................................................................................................ 48
Context Switching ................................................................................................................................ 49
Macro Service ....................................................................................................................................... 49
Application Example of Macro Service ............................................................................................. 50
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
