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UPD784044GCA2: 产品描述16-BIT SINGLE-CHIP MICROCONTROLLER; 文件大小348KB，共90页; 制造商NEC ( Renesas ); 官网地址https://www2.renesas.cn/zh-cn/

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UPD784044GCA2概述

16-BIT SINGLE-CHIP MICROCONTROLLER

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DATA SHEET

PD784044(A), 784046(A)

16-BIT SINGLE-CHIP MICROCONTROLLER

MOS INTEGRATED CIRCUIT

DESCRIPTION

The

PD784046(A) is a model in the

PD784046 subseries within the 78K/IV series. A stricter quality assurance

program applies

PD784046(A) compared to the

PD784046 (standard model). (In terms of NEC’s quality grading,

this is a ”special” grade product.)

The

PD784046(A) is provided with many peripheral hardware functions such as ROM, RAM, I/O port, 10-bit

resolution A/D converter, timer, serial interface, and interrupt functions, in addition to a high-speed, high-performance

CPU.

The

PD784046(A) is under development.

Moreover, a flash memory model,

PD78F4046

Note

, that can operate on the same supply voltage as the mask ROM

model, and many development tools are under development.

Note

Use for functional evaluation only.

The functions are described in detail in the following User’s Manuals. Be sure to read these manuals when

designing your system.

PD784046 Subseries User’s Manual - Hardware : U11515E

78K/IV Series User’s Manual - Instruction

: U10905E

FEATURES

• Higher reliability compared to the

PD784044 and 784046

• Minimum instruction execution time : 160 ns (with 12.5-MHz internal clock) ···

PD784044(A), 784046(A)

200 ns (with 10-MHz internal clock) ···

PD784044(A1), (A2),

784046(A1), (A2)

• I/O port

: 65 lines

• Timer

: 16-bit timer/counter

2 units

16-bit timer

3 units

• A/D converter

: 10-bit resolution

16 channels

• Serial interface

UART/IOE (3-wire serial I/O)

: 2 channels

• Watchdog timer

: 1 channel

• Standby function

HALT/STOP/IDLE mode

• Supply voltage

: V

= 4.5 to 5.5 V

APPLICATION FIELDS

Automotive appliances, etc.

In this document, in addition to the

PD784044(A) and

PD784046(A), the

PD784044(A1), 784044(A2)

784046(A1), and 784046(A2) are also explained. However, unless otherwise specified, the

PD784046(A) is

treated as the representative model throughout this document.

The information in this document is subject to change without notice.

Document No. U13121EJ1V0DS00 (1st edition)

Date Published January 1998 N CP(K)

Printed in Japan

1998

PD784044(A), 784046(A)

CONTENTS

1. DIFFERENCES BETWEEN

PD784044(A) AND 784046(A) ............................................................ 7

2. PIN CONFIGURATION (Top View) ..................................................................................................... 8

3. SYSTEM CONFIGURATION EXAMPLE ...........................................................................................10

4. BLOCK DIAGRAM ............................................................................................................................. 11

5. PIN FUNCTIONS ................................................................................................................................12

5.1

5.2

5.3

Port Pins .................................................................................................................................................... 12

Pins Other Than Port Pins ...................................................................................................................... 14

I/O Circuits of Pins and Processing of Unused Pins .......................................................................... 16

6. CPU ARCHITECTURE .......................................................................................................................18

6.1

6.2

Memory Space .......................................................................................................................................... 18

CPU Registers ........................................................................................................................................... 21

6.2.1

6.2.2

6.2.3

General-purpose registers ............................................................................................................. 21

Control registers ............................................................................................................................. 22

Special function registers (SFRs) .................................................................................................. 23

7. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................29

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

Ports ........................................................................................................................................................... 29

Clock Generation Circuit ......................................................................................................................... 30

Real-Time Output Port ............................................................................................................................. 32

Timer/Counter ........................................................................................................................................... 32

A/D Converter ........................................................................................................................................... 35

Serial Interface .......................................................................................................................................... 36

7.6.1

Asynchronous serial interface/3-wire serial I/O (UART/IOE) ....................................................... 37

Edge Detection Circuit ............................................................................................................................ 39

Watchdog Timer ........................................................................................................................................ 39

8. INTERRUPT FUNCTION....................................................................................................................40

8.1

8.2

8.3

8.4

Interrupt Source ....................................................................................................................................... 40

Vectored Interrupt .................................................................................................................................... 42

Context Switching .................................................................................................................................... 43

Macro Service ........................................................................................................................................... 44

9. LOCAL BUS INTERFACE .................................................................................................................47

9.1

9.2

9.3

9.4

Memory Expansion .................................................................................................................................. 48

Memory Space .......................................................................................................................................... 49

Programmable Wait .................................................................................................................................. 49

Bus Sizing Function ................................................................................................................................. 49

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