SMFV016
Document Title
16M x 8 Bit SmartMedia
TM
Card
Revision History
Revision No
0.0
1.0
SmartMedia
TM
History
Initial issue.
1) Changed t
PROG
Parameter : 1ms(Max.)
→
500µs(Max.)
2) Changed t
BERS
Parameter : 4ms(Max.)
→
3ms(Max.)
3) Changed Input and Output Timing Level 0.8V and 2.0V
→
1.5V
Draft Date
April 10th 1998
July 14th 1998
Remark
Preliminary
Final
1.1
1) Changed t
R
Parameter : 7µs(Max.)
→
10µs(Max.)
2) Changed Nop : 10 cycles(Max.)
→
Main Array 2 cycles(Max.)
Spare Array 3 cycles(Max.)
3) Added CE don’ care mode during the data-loading and reading
t
April 10th 1999
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
SMFV016
16M x 8 Bit SmartMedia
TM
Card
FEATURES
•Single 2.7V~3.6V Supply
•Organization
- Memory Cell Array : (16M + 512K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
•Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
•528-Byte Page Read Operation
- Random Access : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
•Fast Write Cycle Time
- Program time : 200µs(typ.)
- Block Erase time : 2ms(typ.)
•Command/Address/Data Multiplexed I/O port
•Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•Reliable CMOS Floating-Gate Technology
- Endurance : 1M Program/Erase Cycles
- Data Retention : 10 years
•Command Register Operation
•22pad SmartMedia
TM
(SSFDC)
SmartMedia
TM
GENERAL DESCRIPTION
The SMFV016 is a 16M(16,777,216)x8bit NAND Flash Memory
with a spare 512K(524,288)x8bit. Its NAND cell provides the
most cost-effective solution for the solid state mass storage
market. A program operation programs the 528-byte page in
typically 200µs and an erase operation can be performed in typ-
ically 2ms on a 16K-byte block. Data in the page can be read
out at 50ns cycle time per byte. The I/O pins serve as the ports
for address and data input/output as well as command inputs.
The on-chip write controller automates all program and erase
functions including pulse repetition, where required, and inter-
nal verify and margining of data. Even the write-intensive sys-
tems can take advantage of the SMFV016′s extended reliability
of 1,000,000 program/erase cycles by providing either
ECC(Error Correcting Code) or real time mapping-out algo-
rithm. These algorithms have been implemented in many mass
storage applications and also the spare 16 bytes of a page
combined with the other 512 bytes can be utilized by system-
level ECC.
The SMFV016 is an optimum solution for large nonvolatile stor-
age applications such as solid state file storage, digital voice
recorder, digital still camera and other portable applications
requiring non-volatility.
SmartMedia
TM
CARD(SSFDC)
PIN DESCRIPTION
Pin Name
22 V
CC
21 CE
20 RE
19 R/B
18 GND
17 V
CC
16 I/O
7
15 I/O
6
14 I/O
5
13 I/O
4
12 V
CC
11
1
12
22
1
2
3
4
5
6
7
8
9
V
SS
CLE
ALE
WE
WP
I/O
0
I/O
1
I/O
2
I/O
3
Pin Function
Data Input/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ground
Ready/Busy output
Power(2.7V~3.6V)
Ground
No Connection
I/O0 ~ I/O7
CLE
ALE
CE
RE
WE
WP
GND
R/B
16MB - 3.3
10 V
SS
11 V
SS
22 PAD
SmartMedia
TM
V
CC
V
SS
N.C
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
2
SMFV016
Figure 1. FUNCTIONAL BLOCK DIAGRAM
V
CC
V
SS
A
9
- A
23
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Y-Gating
2nd half Page Register & S/A
128M + 4M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 32768
1st half Page Register & S/A
SmartMedia
TM
A
0
- A
7
A
8
Command
Command
Register
Y-Gating
I/O Buffers & Latches
V
CC
V
SS
I/0 0
I/0 7
CE
RE
WE
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block(=32 Row)
(16K + 512) Byte
32K Row
(=1024 Block)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
= (16K + 512) Bytes
1 Device = 528B x 32Pages x 1024 Blocks
= 132 Mbits
8 bit
16 Byte Column
512B column
Page Register
512 Byte
I/O 0
1st Cycle
2nd Cycle
3rd Cycle
A
0
A
9
A
17
I/O 1
A
1
A
10
A
18
I/O 2
A
2
A
11
A
19
16 Byte
I/O 3
A
3
A
12
A
20
I/O 0 ~ I/O 7
I/O 4
A
4
A
13
A
21
I/O 5
A
5
A
14
A
22
I/O 6
A
6
A
15
A
23
I/O 7
A
7
A
16
*X
Column Address
Row Address
(Page Address)
NOTE
: Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A
8
is initially set to "Low" or "High" by the 00h or 01h Command.
* X can be High or Low.
3
SMFV016
PRODUCT INTRODUCTION
SmartMedia
TM
The SMFV016 is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows by 528 columns. Spare sixteen columns are located
from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages
formed by one NAND structures, totaling 8488 NAND structures of 16 cells. The array organization is shown in Figure 2. The pro-
gram and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array
consists of 1024 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the SMFV016.
The SMFV016 has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to
future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except
for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address
loading. The 16M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column
address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles
following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device opera-
tions are selected by writing specific commands into the command register. Table 1 defines the specific commands of the SMFV016.
Table 1. COMMAND GNDTS
Function
Sequential Data Input
Read 1
Read 2
Read ID
Reset
Page Program
Block Erase
Read Status
1st. Cycle
80h
00h/01h
(1)
50h
90h
FFh
10h
60h
70h
2nd. Cycle
-
-
-
-
-
-
D0h
-
O
O
Acceptable Command during Busy
NOTE
: 1. The 00H command defines starting address of the 1st half of registers.
The 01H command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
4
SMFV016
PIN DESCRIPTION
Command Latch Enable(CLE)
SmartMedia
TM
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
REA
after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
5
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