DATA SHEET
µ
PD784218, 784218Y
16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD784218 is a member of the
µ
PD784218 Subseries of the 78K/IV Series. In addition to a high-speed and
high-performance CPU, the
µ
PD784218 incorporates a variety of peripheral hardware such as ROM, RAM, I/O ports,
8-bit resolution A/D and D/A converters, timers, serial interfaces, real-time output ports, and an interrupt function.
The
µ
PD784218Y
Note
is the
µ
PD784218 Subseries with a multi-master supporting I
2
C bus interface added.
Flash memory versions, the
µ
PD78F4218 and 78F4218Y, which can operate in the same voltage range as the
mask ROM versions, and various development tools are also available.
Note
Under development
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µ
PD784218, 784218Y Subseries User’s Manual Hardware: U12970E
78K/IV Series User’s Manual Instructions:
U10905E
FEATURES
• On-chip ROM correction function
• Inherits peripheral functions of
µ
PD78078Y Subseries
• Minimum instruction execution time
160 ns
(@ f
XX
= 12.5 MHz operation with main system clock)
61
µ
s
(@ f
XT
= 32.768 kHz operation with subsystem clock)
• Internal high-capacity memory
· ROM: 256 KB
· RAM: 12,800 bytes
• I/O ports: 86
• Timer/counters: 16-bit timer/event counter
×
1 unit
8-bit timer/event counter
×
6 units
• Serial interfaces: 3 channels
UART/IOE (3-wire serial I/O): 2 channels
CSI (3-wire serial I/O, multi-master supporting I
2
C
bus
Note
): 1 channel
Note
µ
PD784218Y only
Unless otherwise specified, references in this document to the
µ
PD784218 refer to the
µ
PD784218 and
the
µ
PD784218Y.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• Standby function
HALT/STOP/IDLE mode
In power-saving mode: HALT/IDLE mode (with
subsystem clock)
• Clock division function
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Clock output function
Selectable from f
XX
, f
XX
/2, f
XX
/2
2
, f
XX
/2
3
, f
XX
/2
4
,
f
XX
/2
5
, f
XX
/2
6
, f
XX
/2
7
, f
XT
• Buzzer output function
Selectable from f
XX
/2
10
, f
XX
/2
11
, f
XX
/2
12
, f
XX
/2
13
• A/D converter: 8-bit resolution
×
8 channels
• D/A converter: 8-bit resolution
×
2 channels
• Supply voltage: V
DD
= 2.2 to 5.5 V
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U12304EJ2V0DS00 (2nd edition)
Date Published March 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 2000
µ
PD784218, 784218Y
APPLICATIONS
Cellular phones, personal handy phone system (PHS), cordless telephones, CD-ROM, AV equipment
ORDERING INFORMATION
Part Number
Package
100-pin plastic LQFP (fine pitch) (14
×
14 mm)
100-pin plastic QFP (14
×
20 mm)
100-pin plastic QFP (14
×
20 mm)
Internal ROM Internal RAM
(Bytes)
(Bytes)
12,800
12,800
12,800
12,800
µ
PD784218GC-×××-8EU
µ
PD784218GF-×××-3BA
µ
PD784218YGF-×××-3BA
Note
Note
Under development
256 K
256 K
256 K
256 K
µ
PD784218YGC-×××-8EU
Note
100-pin plastic LQFP (fine pitch) (14
×
14 mm)
Remark
×××
indicates ROM code suffix.
2
Data Sheet U12304EJ2V0DS00
µ
PD784218, 784218Y
78K/IV SERIES LINEUP
: Under mass production
: Under development
I
2
C bus supported
Multi-master I
2
C bus supported
µ
PD784038Y
µ
PD784038
µ
PD784225Y
µ
PD784225
80-pin, ROM correction added
Multi-master I
2
C bus supported
Standard models
µ
PD784026
Enhanced
A/D converter,
16-bit timer, and
power management
Enhanced internal memory capacity
Pin-compatible with the
µ
PD784026
Multi-master I
2
C bus supported
µ
PD784216Y
µ
PD784216
100-pin, enhanced I/O and
internal memory capacity
µ
PD784218Y
µ
PD784218
Enhanced internal memory
capacity, ROM correction added
µ
PD784054
µ
PD784046
ASSP models
µ
PD784956A
For DC inverter control
On-chip 10-bit A/D converter
µ
PD784938
Enhanced functions of the
µ
PD784908, enhanced
internal memory capacity,
ROM correction added.
Multi-master I
2
C bus supported
µ
PD784908
On-chip IEBus
TM
controller
µ
PD784928Y
µ
PD784915
Software servo control
On-chip analog circuit for VCRs
Enhanced timer
µ
PD784928
Enhanced functions
of the
µ
PD784915
µ
PD784967
On-chip FIP controller/driver
Data Sheet U12304EJ2V0DS00
3
µ
PD784218, 784218Y
OVERVIEW OF FUNCTIONS (1/2)
Part Number
Item
Number of basic instructions
(mnemonics)
General-purpose registers
Minimum instruction execution
time
Internal
memory
Memory space
I/O ports
Total
CMOS input
CMOS I/O
N-ch open-drain I/O
Pins with
Pins with pull-up
ancillary
resistor
functions
Note 2
LED direct
drive outputs
Middle-
voltage pins
Real-time output port
Timer/counters
ROM
RAM
113
8 bits
×
16 registers
×
8 banks, or 16 bits
×
8 registers
×
8 banks (memory mapping)
• 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@ f
XX
= 12.5 MHz operation with main system clock)
• 61
µ
s (@ f
XT
= 32.768 kHz operation with subsystem clock)
256 KB
12,800 bytes
1 MB with program and data spaces combined
86
8
72
6
70
22
6
4 bits
×
2, or 8 bits
×
1
Timer/event counter:
(16-bit)
Timer counter
×
1
Pulse output
Capture/compare register
×
2 • PPG output
• Square wave output
• One-shot pulse output
Pulse output
• PWM output
• Square wave output
Pulse output
• PWM output
• Square wave output
Pulse output
• PWM output
• Square wave output
Pulse output
• PWM output
• Square wave output
Pulse output
• PWM output
• Square wave output
Pulse output
• PWM output
• Square wave output
µ
PD784218,
µ
PD784218Y
Note 1
Timer/event counter 1: Timer counter
×
1
(8-bit)
Compare register
×
1
Timer/event counter 2: Timer counter
×
1
(8-bit)
Compare register
×
1
Timer/event counter 5: Timer counter
×
1
(8-bit)
Compare register
×
1
Timer/event counter 6: Timer counter
×
1
(8-bit)
Compare register
×
1
Timer/event counter 7: Timer counter
×
1
(8-bit)
Compare register
×
1
Timer/event counter 8: Timer counter
×
1
(8-bit)
Compare register
×
1
Serial interfaces
A/D converter
D/A converter
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O, multi-master supporting I
2
C bus
Note 3
): 1 channel
8-bit resolution
×
8 channels
8-bit resolution
×
2 channels
Notes 1.
Under development
2.
The pins with ancillary functions are included in the I/O pins.
3.
µ
PD784218Y only
4
Data Sheet U12304EJ2V0DS00
µ
PD784218, 784218Y
OVERVIEW OF FUNCTIONS (2/2)
Part Number
Item
Clock output
Buzzer output
Watch timer
Watchdog timer
Standby
Interrupts
Hardware sources
Software sources
Non-maskable
Maskable
Selectable from f
XX
, f
XX
/2, f
XX
/2
2
, f
XX
/2
3
, f
XX
/2
4
, f
XX
/2
5
, f
XX
/2
6
, f
XX
/2
7
, f
XT
Selectable from f
XX
/2
10
, f
XX
/2
11
, f
XX
/2
12
, f
XX
/2
13
1 channel
1 channel
• HALT/STOP/IDLE modes
• In low-power consumption mode (with subsystem clock): HALT/IDLE mode
29 (internal: 20, external: 9)
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 19, external: 8
• 4 programmable priority levels
• 3 service modes: vectored interrupt/macro service/context switching
Supply voltage
Package
V
DD
= 2.2 to 5.5 V
100-pin plastic LQFP (fine pitch) (14
×
14 mm)
100-pin plastic QFP (14
×
20 mm)
µ
PD784218,
µ
PD784218Y
Note
Note
Under development
Data Sheet U12304EJ2V0DS00
5
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