DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD8871
10680 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The
µ
PD8871 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
µ
PD8871 has 3 rows of 10680 pixels, and each row has a single-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color
image scanners, color facsimiles and so on.
FEATURES
•
Valid photocell
•
Photocell pitch
•
Photocell size
•
Line spacing
•
Color filter
•
Resolution
:
: 10680 pixels
×
3
: 4
µ
m
: 4
×
4
µ
m
2
: 32
µ
m (8 lines) Red line - Green line, Green line - Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour)
: 48 dot/mm A4 (210
×
297 mm) size (shorter side)
1200 dpi US letter (8.5”
×
11”) size (shorter side)
7
•
Drive clock level : CMOS output under 5 V operation
•
Data rate
•
Power supply
•
On-chip circuits
::
: 10 MHz Max.
: +12 V
: Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
µ
PD8871CY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15329EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
The mark
shows major revised points.
2001
µ
PD8871
BLOCK DIAGRAM
V
OD
29
GND
1
GND
16
φ
2
22
φ
1
19
V
OUT
1
(Blue)
30
CCD analog shift register
Transfer gate
······
Photocell
(Blue)
18
V
OUT
2
(Green)
31
CCD analog shift register
Transfer gate
······
Photocell
(Green)
17
S10679
S10680
D65
D66
D67
φ
TG1
(Blue)
D14
D64
S1
S2
V
OUT
3
(Red)
32
CCD analog shift register
Transfer gate
······
Photocell
(Red)
S10679
S10680
D65
D66
D67
φ
TG2
(Green)
D14
D64
S1
S2
15
S10679
S10680
D65
D66
D67
φ
TG3
(Red)
D14
D64
S1
S2
2
4
3
11
14
φ
CLB
φ
RB
φ
1L
φ
2
φ
1
2
Data Sheet S15329EJ2V0DS
µ
PD8871
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
•
µ
PD8871CY
Ground
Reset feed-through level
clamp clock
Last stage shift register clock 1
Reset gate clock
No connection
Internal connection
Internal connection
No connection
No connection
No connection
Shift register clock 2
Internal connection
Internal connection
Shift register clock 1
Transfer gate clock 3
(for Red)
Ground
GND
1
2
32
31
V
OUT
3
V
OUT
2
V
OUT
1
V
OD
NC
IC
IC
NC
NC
NC
Output signal 3 (Red)
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
No connection
Internal connection
Internal connection
No connection
No connection
No connection
Shift register clock 2
Internal connection
Internal connection
Shift register clock 1
Transfer gate clock 1
(for Blue)
Transfer gate clock 2
(for Green)
φ
CLB
1
1
φ
1L
φ
RB
NC
IC
IC
NC
NC
NC
1
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Green
9
10
11
12
13
14
15
16
φ
2
IC
IC
Blue
Red
φ
2
IC
IC
10680
10680
φ
TG3
GND
10680
φ
1
φ
1
φ
TG1
φ
TG2
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Data Sheet S15329EJ2V0DS
3
µ
PD8871
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
4
µ
m
2
µ
m
2
µ
m
Blue photocell array
8 lines
(32
µ
m)
4
µ
m
Channel stopper
4
µ
m
Green photocell array
8 lines
(32
µ
m)
Aluminum
shield
4
µ
m
Red photocell array
4
Data Sheet S15329EJ2V0DS
µ
PD8871
ABSOLUTE MAXIMUM RATINGS (T
A
=
+
25°C)
°
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp
clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
Note
Symbol
V
OD
V
φ
1
, V
φ
2
, V
φ
1L
V
φ
RB
V
φ
CLB
Ratings
−0.3
to
+15
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
0 to
+60
−40
to
+70
Unit
V
V
V
V
V
φ
TG1
to V
φ
TG3
T
A
T
stg
V
°C
°C
Note
Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+
25°C)
°
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock
high level
Reset feed-through level clamp clock
low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
V
φ
TG1H
to V
φ
TG3H
V
φ
TG1L
to V
φ
TG3L
f
φ
RB
4.75
−0.3
−
V
φ
1H
0
2.0
Note
Symbol
V
OD
V
φ
1H
, V
φ
2H
, V
φ
1LH
V
φ
1L
, V
φ
2L
, V
φ
1LL
V
φ
RBH
V
φ
RBL
V
φ
CLBH
Min.
11.4
4.75
−0.3
4.5
−0.3
4.5
−0.3
Typ.
12.0
5.0
0
5.0
0
5.0
Max.
12.6
5.5
+0.25
5.5
+0.5
5.5
+0.5
V
φ
1H
Note
Unit
V
V
V
V
V
V
V
φ
CLBL
0
V
V
V
MHz
+0.15
10.0
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
),
Image lag can increase.
Data Sheet S15329EJ2V0DS
5
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