DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD98401A
ATM SAR CHIP
DESCRIPTION
The
µ
PD98401A (NEASCOT-S15
TM
) is a high-performance SAR chip that segments and reassembles ATM cells.
This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,
network hub, or router. The
µ
PD98401A conforms to the ATM Forum Recommendation, and provides the functions
of the AAL-5 SAR sublayer and ATM layer.
The
µ
PD98401A is compatible with its predecessor,
µ
PD98401, in terms of hardware and software.
Functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing your
system.
µ
PD98401A User’s Manual: S12054E
FEATURES
• Conforms to ATM Forum
• AAL-5 SAR sublayer and ATM layer functions
• Hardware support of AAL-5 processing
• Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function
• Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic
• Supports up to 32K virtual channels (VC)
• Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to
set different transmission rate for each VC
• Interface and commands for controlling PHY device
• Employs “UTOPIA interface” as cell data interface with PHY device
- Octet-level handshake
- Cell-level handshake
• 32-bit general-purpose bus interface
• High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst)
• JTAG boundary scan test function (IEEE1149.1)
• CMOS technology
• +5 V single power source
Remark
In this document, an active low pin is indicated by
×××_B
(_B after a pin name).
The information in this document is subject to change without notice.
Document No. S12100EJ3V0DS00 (3rd edition)
Date Published February 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997
µ
PD98401A
PIN NAMES
ABRT_B
AD31_AD0
ASEL_B
ATTN_B
CA17-CA0
CD31-CD0
CLK
COE_B
CPAR3-CPAR0
CWE_B
DBMD
DBMF
DBML
DBVC
DBMR
DR/W_B
ERR_B
FULL_B/TxCLAV
GND
GNT_B
INITD
INTR_B
JCK
JDI
JDO
JMS
JRST_B
OE_B
PAR3-PAR0
: Abort
: Address/Data
: Slave Address Select
: Attention/Burst Frame
: Control Memory Address
: Control Memory Data
: Clock
: Control Memory Output Enable
: Control Memory Parity
: Control Memory Write Enable
: DMA Bus Monitor Data
: DMA Bus Monitor First
: DMA Bus Monitor Last
: DMA Bus Monitor VC
: DMA Bus Monitor Remaining
: DMA Read/Write
: Error
: PHY Buffer Ful
: Ground
: Grant
: Initialization Disable
: Interrupt
: JTAG Test Pin
: JTAG Test Pin
: JTAG Test Pin
: JTAG Test Pin
: JTAG Test Pin
: Output Enable
: Bus Parity
PHCE_B
PHINT_B
PHOE_B
PHRW_B
RCLK
RDY_B
RENBL_B
RSOC
RST_B
Rx7-Rx0
SLE_B
SIZE2-SIZE0
SR/W_B
TCLK
TENBL_B
TSOC
TRF_B
Tx7-Tx0
V
DD
: PHY Chip Enable
: PHY Interrupt
: PHY Output Enable
: PHY Read/Write
: Receive Clock
: Target Ready
: Receive Enable
: Receive Start Cell
: Reset
: Receive Data Bus
: Slave Select
: Burst Size
: Slave Read/Write
: Transmit Clock
: Transmit Enable
: Transmit Start of Cell
: Delay Select
: Transmit Data Bus
: Power Supply
CBE_B3_CBE_B0 : Local Port Byte Enable
EMPTY_B/RxCLAV : PHY Output Buffer Empty
Data Sheet S12100EJ3V0DS00
5
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