DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD98404
ADVANCED ATM SONET FRAMER
DESCRIPTION
The
µ
PD98404 NEASCOT-P30
TM
is an LSI for ATM applications, which can be used in ATM adapter boards for
connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches. This LSI
provides the TC sub-layer functions in the SONET/SDH-base physical layer within the ATM protocol defined by the
ATM Forum’s UNI3.1 recommendations.
This product’s main functions include transmission functions such as mapping of ATM cells sent from the ATM
layer to the payload field in a 155 Mbps SONET STS-3c/SDH STM-1 frame and transmission to PMD (Physical Media
Dependent) sub-layer in the physical layer. Its reception functions include separation of the overhead from the ATM
cells in data streams received from PMD sub-layer and transmission of the ATM cells to the ATM layer. In addition,
this LSI includes a clock recovery function that extracts a reception sync clock from bit streams in received data and
a clock synthesis function that generates a clock for transmissions.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µ
PD98404 User’s Manual: S11821E
FEATURES
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On-chip clock recovery/clock synthesis functions
Provides TC sub-layer function for the ATM protocol’s physical layer
Supported frame formats include 155 Mbps SONET STS-3c/SDH STM-1
Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995)
Supports three UTOPIA interfaces:
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Single PHY octet-level handshaking
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Single PHY cell-level handshaking
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Multi PHY mode
Selectable to drop/bypass unassigned cells
On-chip internal loopback functions for PMD layer loopback and ATM layer loopback
Supports two PMD interfaces: serial and parallel
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155.52 Mbps serial interface
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19.44 MHz parallel interface
Provides registers for writing/reading overhead information
SOH (section overhead) :J0 byte, Z0 (first and second) bytes, F1 byte
LOH (line overhead)
:K1 byte, K2 byte
POH (path overhead)
:F2 byte, C2 byte, H4 byte
Provides pseudo error frame transmit function for various errors
Supports JTAG boundary scan test function (IEEE 1149.1)
CMOS technology
+3.3 V single power supply
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
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Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S11822EJ4V0DS00 (4th edition)
Date Published May 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 1999
µ
PD98404
• Provides abundant OAM (Operation and Maintenance) functions
Receive side
Transmit side
•
Transmission of various alarm data
* Source-triggered automatic loopback transmission
Line RDI, Path RDI
Line REI, Path REI
* Command-specified transmission
Line AIS, Path AIS
•
Pseudo error generation frame transmit functions
LOS generated frame
OOF, LOF generated frame
LOP generated frame
OCD, LCD generated frame
B1 error generated frame
B2 error generated frame
B3 error generated frame
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Detection of alarm and fault signals
LOS (Loss Of Signal)
OOF (Out Of Frame)
LOF (Loss Of Frame)
LOP (Loss Of Pointer)
OCD (Out of Cell Delineation)
LOC (Loss Of Cell delineation)
Line RDI, Path RDI
Line AIS, Path AIS
Detection and display of quality loss sources
B1 error, B2 error, B3 error,
Line REI, Path-REI
On-chip error counters
B1 byte error counter (16-bit)
B2 byte error counter (20-bit)
B3 byte error counter (16-bit)
Line REI error counter (20-bit)
Path REI error counter (16-bit)
Rx Frequency justification processing counter (12-bit)
HEC error drop cell counter (20-bit)
FIFO overflow drop cell counter (20-bit)
Idle cell counter (20-bit)
ORDERING INFORMATION
Part number
Package
144-pin plastic QFP (fine pitch) (20
×
20 mm)
µ
PD98404GJ-KEU
2
Data Sheet S11822EJ4V0DS00
微控制器 MCU
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